Abstract
Data Driven Dynamic Logic (D3L) achieves a considerably energy saving, over conventional Domino Logic, by removing the clock signal: the control of the precharge and evaluation phases is managed only by input data. Unfortunately, this advantage is typically obtained at the expense of speed performances and consequently affecting the Energy-Delay Product (EDP). This paper presents a novel technique to design D3L parallel prefix adders considerably reducing speed penalties. Moreover, a new design style, named Splith-Path D3L, is introduced to overcome the limits of standard D3L. When applied to a 32-bit Kogge-Stone adder realized with the STMicroelectronics 65nm 1V CMOS technology, the proposed technique leads to an EDP 25% and 20% lower than the standard Domino Logic and the conventional D3L counterparts, respectively.
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References
Shalem, R., John, E., John, L.K.: A novel low power energy recovery full adder cell. In: Proceedings of the 9th Great Lakes Symposium on VLSI, Ypsilanti, Michigan (USA), March 4-6, pp. 380–383 (1999)
Kawaguchi, H., Sakurai, T.: A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J. Solid-State Circuits 33(5), 807–811 (1998)
Rafati, R., Fakhraie, S.M., Smith, K.C.: A 16-Bit Barrel-Shifter Implemented in Data-Driven Dynamic Logic (D3L). IEEE Transaction on Circuits and Systems I 53(10), 2194–2202 (2006)
Frustaci, F., Lanuzza, M., Zicari, P., Perri, S., Corsonello, P.: Designing High Speed Adders in Power-Constrained Environments. IEEE Transaction on Circuits and Systems. II. Express Brief 56(2), 172–176 (2009)
Kim, J., Lee, K., Yoo, H.-J.: A 372ps 64-bit Adder using Fast Pull-up Logic in 0.18-um CMOS. In: Proceedings of the 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of KOS, Greece, May 21-24, pp. 13–16 (2006)
Kao, S., Zlatanovici, R., Nikolic, B.: A 240ps 64b Carry-Lookahead Adder in 90nm CMOS. In: Proceedings of the2006 IEEE International Solid-State Circuits Conference, San Francisco, California, USA, February 6-9, pp. 1735–1744 (2006)
Kogge, P.M., Stone, H.S.: A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Transactions on Computers 22, 786–793 (1973)
Brent, R.P., Kung, H.T.: A Regular Layout for Parallel Adders. IEEE Transactions on Computers C-31, 260–264 (1982)
Knowles, S.: A family of adders. In: Proceedings of the 15th IEEE Symposium on Computer Arithmetic, Vail, Colorado (USA), June 11-13, pp. 277–281 (2001)
Elgebaly, M., Sachdev, M.: A leakage tolerant energy efficient wide domino circuit technique. In: Proceedings of the 45th Midwest Symposium on Circuits and Systems, Tulsa, Oklaomah (USA), August 4-7, vol. 1, pp. 487–490 (2002)
Solomatnikov, A., Somasekhar, D., Roy, K., Koh, C.-K.: Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(4), 469–476 (2002)
Sutherland, I., Sproull, R., Harris, D.: Logical Effort. Morgan Kaufmann Publishers, San Francisco (1999)
STMicroelectronics CORE65LPSVT_1.00V 4.0 Standard Cell Library User Manual & Data Book
Croon, J.A., Sansen, W., Maes, H.E.: Matching Properties of Deep Sub-Micron MOS Transistors. Springer, Heidelberg (2005)
Srivasta, A., Sylvester, D., Blaauw, D.: Statistical Analysis and Optimization for VLSI: Timing and Power. Springer, Heidelberg (2005)
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Frustaci, F., Lanuzza, M. (2010). A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_40
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DOI: https://doi.org/10.1007/978-3-642-11802-9_40
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11801-2
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