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Reconfigurable Computing: Architectures, Tools and Applications

6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings

  • Conference proceedings
  • © 2010

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Editors:
  1. Phaophak Sirisuk

    1. Department of Electronic Engineering, Mahanakorn University of Technology, Bangkok, Thailand

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  2. Fearghal Morgan

    1. Department of Electronic Engineering, National University of Ireland, Galway, Ireland

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  3. Tarek El-Ghazawi

    1. Department of Electrical and Computer Engineering, The George Washington University, Washington, USA

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  4. Hideharu Amano

    1. Department of Information and Computer Science, Yokohama, Keio University, Kanagawa, Japan

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  • Fast track conference proceedings
  • State of the art paper on reconfigurable computing (RC)
  • Up to date research

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 5992)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

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Conference proceedings info: ARC 2010.

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About this book

Recon?gurable computing (RC) systems have generated considerable interest in the embedded and high-performance computing communities over the past two decades, with ?eld programmable gate arrays (FPGAs) as the leading techn- ogy at the helm of innovation in this discipline. Achieving orders of magnitude performance and power improvements using FPGAs over traditional microp- cessorsis not uncommon for well-suitedapplications. But even with two decades of research and technological advances, FPGA design still presents a subst- tial challenge and often necessitates hardware design expertise to exploit its true potential. Although the challenges to address the design productivity - sues are steep, the promise and the potential of the RC technology in terms of performance, power, size, and versatility continue to attract application design engineers and RC researchers alike. The International Symposium on Applied Recon?gurable Computing (ARC) aims to bring together researchers and practitioners of RC systems with an emphasis on practical applications and design methodologies of this promising technology. This year’s ARC symposium (The sixth ARC symposium) was held in Bangkok, Thailand during March 17–19, 2010, and attracted papers in three primary focus areas:RC applications, RC architectures, and RC design meth- ologies.

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Table of contents (45 papers)

  1. Front Matter

    Pages I-XIV
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  3. Session 1: Architectures 1

    1. Generic Systolic Array for Run-Time Scalable Cores

      • Andrés Otero, Yana E. Krasteva, Eduardo de la Torre, Teresa Riesgo
      Pages 4-16

    2. Virtualization within a Parallel Array of Homogeneous Processing Units

      • Marc Stöttinger, Alexander Biedermann, Sorin Alexander Huss
      Pages 17-28

    3. Feasibility Study of a Self-healing Hardware Platform

      • Michael Reibel Boesen, Pascal Schleuniger, Jan Madsen
      Pages 29-41

  4. Session 2: Applications 1

    1. Application-Specific Signatures for Transactional Memory in Soft Processors

      • Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
      Pages 42-54

    2. Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems

      • Christopher Claus, Rehan Ahmed, Florian Altenried, Walter Stechele
      Pages 55-67

    3. Parametric Encryption Hardware Design

      • Adrien Le Masle, Wayne Luk, Jared Eldredge, Kris Carver
      Pages 68-79

    4. A Reconfigurable Implementation of the Tate Pairing Computation over GF(2m)

      • Weibo Pan, William Marnane
      Pages 80-91

  5. Session 3: Architectures 2

    1. Application Specific FPGA Using Heterogeneous Logic Blocks

      • Husain Parvez, Zied Marrakchi, Habib Mehrez
      Pages 92-109

    2. Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip

      • Mouna Baklouti, Philippe Marquet, Jean Luc Dekeyser, Mohamed Abid
      Pages 110-121

    3. A Dedicated Reconfigurable Architecture for Finite State Machines

      • Johann Glaser, Markus Damm, Jan Haase, Christoph Grimm
      Pages 122-133

    4. MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment

      • Daisaku Seto, Minoru Watanabe
      Pages 134-144

  6. Session 4: Applications 2

    1. An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme

      • Abdulhadi Shoufan
      Pages 145-156

    2. A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs

      • Antonio Roldao Lopes, George A. Constantinides
      Pages 157-168

    3. Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods

      • David Boland, George A. Constantinides
      Pages 169-181

    4. Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA

      • Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides
      Pages 182-193

  7. Session 5: Design Tools 1

    1. 3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices

      • Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev
      Pages 194-206
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Other volumes

  1. Reconfigurable Computing: Architectures, Tools and Applications

Editors and Affiliations

  • Department of Electronic Engineering, Mahanakorn University of Technology, Bangkok, Thailand

    Phaophak Sirisuk

  • Department of Electronic Engineering, National University of Ireland, Galway, Ireland

    Fearghal Morgan

  • Department of Electrical and Computer Engineering, The George Washington University, Washington, USA

    Tarek El-Ghazawi

  • Department of Information and Computer Science, Yokohama, Keio University, Kanagawa, Japan

    Hideharu Amano

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