Abstract
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challenges facing researchers. This work describes the FPGA implementation of two reconfigurable and flexible communication networks integrated into mppSoC. An mppSoC system is an SIMD massively parallel processing System on Chip designed for data-parallel applications. Its most distinguished features are its parameterization and the reconfigurability of its interconnection networks. This reconfigurability allows to establish one configuration with a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved. Experimental results for mppSoC with different communication configurations demonstrate the performance of the used reconfigurable networks and the effectiveness of algorithm mapping through reconfiguration.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Ginhac, D., Dubois, J., Paindavoine, M., Heyrman, B.: An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing. Eurasip J. on Embedded Systems 2008 (2008)
Fatemi, H., Mesman, B., Corporaal, H., Basten, T., Kleihorst, R.: RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications. J. Embedded Computing 2, 167–179 (2006)
Flynn, M.J.: Some computer organizations and their effectiveness. IEEE Trans. Comput. 21, 948–960 (1972)
Parhami, B.: Introduction to Parallel Processing: Algorithms and Architectures. Kluwer Academic Publishers, Dordrecht (1999)
Michael Hord, R.: The Illiac IV the first supercomputer. Computer Science Press, Rockville (1982)
Xu, X., Ziavras, S.G., Chang, T.G.: An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds.) EUC 2005. LNCS, vol. 3824, pp. 458–468. Springer, Heidelberg (2005)
Schurz, F., Fey, D.: A programmable parallel processor architecture in FPGAs for image processing sensors. In: Proc. IDPT 2007 (2007)
Siege, H.J., Wang, L., So, J.E., Maheswaran, M.: Data parallel algorithms. ECE Technical Reports (1994)
Stone, H.: Parallel computers. In: Stone, H. (ed.) Introduction to Computer Architecture, Chicago, pp. 327–355 (1975)
Wang, H., Walker, R.A.: Implementing a Scalable ASC Processor. In: Proc. International Symposium on Parallel and Distributed Processing, IPDPS. IEEE Computer Society, Los Alamitos (2003)
Baklouti, M., Marquet, P., Abid, M., Dekeyser, J.L.: A design and an implementation of a parallel based SIMD architecture for SoC on FPGA. In: Proc. DASIP, Bruxelles, Belgium (2008)
Lee, M.-H., Singh, H., Lu, G., Bagherzadeh, N., Kurdahi, F.J., Filho, E.M.C., Alves, V.C.: Design and Implementation of the MorphoSys Reconfigurable Computing Processor. In: VLSI Signal Processing, pp. 147–164 (2000)
Kumar, P.: An FPGA Based SIMD Architecture Implemented with 2D Systolic Architecture for Image Processing (2006), SSRN, http://ssrn.com/abstract=944733
Eklund, S.E.: A Massively Parallel Architecture for Linear Machine Code Genetic Programming. In: Liu, Y., Tanaka, K., Iwata, M., Higuchi, T., Yasunaga, M. (eds.) ICES 2001. LNCS, vol. 2210, pp. 216–224. Springer, Heidelberg (2001)
Blank, T.: The MasPar MP-1 architecture. In: Proc. IEEE Compcon Spring 1990, pp. 20–24. IEEE Society Press, San Francisco (1990)
Altera, http://www.altera.com
OpenCores, miniMIPS overview, http://www.opencores.org/projects.cgi/web/minimips
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Baklouti, M., Marquet, P., Dekeyser, J.L., Abid, M. (2010). Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. In: Sirisuk, P., Morgan, F., El-Ghazawi, T., Amano, H. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2010. Lecture Notes in Computer Science, vol 5992. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12133-3_12
Download citation
DOI: https://doi.org/10.1007/978-3-642-12133-3_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-12132-6
Online ISBN: 978-3-642-12133-3
eBook Packages: Computer ScienceComputer Science (R0)