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A Modified Merging Approach for Datapath Configuration Time Reduction

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Reconfigurable Computing: Architectures, Tools and Applications (ARC 2010)

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Abstract

This paper represents a modified datapath merging technique to amortize the configuration latency of mapping datapaths on reconfigurable fabric in Run-Time Reconfigurable Systems (RTR). This method embeds together the different Data Flow Graphs (DFGs), corresponding to the loop kernels to create a single datapath (merged datapath) instead of multiple datapaths. The DFGs are merged in steps where each step corresponds to combining a DFG onto the merged datapath. Afterwards, the method combines the resources inside the merged datapath to minimize the configuration time by employing the maximum weighted clique technique. The proposed merging technique is evaluated using the Media-bench suit workloads. The results indicate that our technique outperforms previous HLS approaches aimed at RTR systems and reduces the datapath configuration time up to 10%.

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References

  1. Wenyin, F., Compton, K.: An Execution Environment for Reconfigurable Computing. In: Proc. of 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), CA, USA, April 2005, pp. 149–158 (2005)

    Google Scholar 

  2. Li, Z.: Configuration Management Techniques for Reconfigurable Computing.: Ph.D. Thesis. Northwestern University (June 2002)

    Google Scholar 

  3. Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K.L.M., Kuzmanov, G.K., Panainte, E.M.: The Molen Polymorphic Processor. IEEE Transactions on Computers (TC) 53(11), 1363–1375 (2004)

    Article  Google Scholar 

  4. Ghiasi, S., Nahapetian, A., Sarrafzadeh, M.: An Optimal Algorithm for Minimizing Runtime Reconfiguration Delay. ACM Transactions on Embedded Computing Systems (TECS) 3(2), 237–256 (2004)

    Article  Google Scholar 

  5. Rollmann, M., Merker, R.: A Cost Model for Partial Dynamic Reconfiguration. In: Proc. of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Greece, July 2008, pp. 182–186 (2008)

    Google Scholar 

  6. Farshadjam, F., Dehghan, M., Fathy, M., Ahmadi, M.: A new compression based approach for reconfiguration overhead reduction in Virtex-based RTR systems. Elsevier Journal on Computers &Electrical Engineering 32(4), 322–347 (2006)

    Article  MATH  Google Scholar 

  7. Qu, Y., Tiensyrj, K., Soininen, J.P., Nurmi, J.: Design Flow Instantiation for Run-Time Reconfigurable Systems. EURASIP Journal on Embedded Systems (TECS) 2(11), 1–9 (2008)

    Article  Google Scholar 

  8. Yankova, Y.D., Kuzmanov, G.K., Bertels, K.L.M., Gaydadjiev, G.N., Lu, Y., Vassiliadis, S.: DWARV: DelftWorkbench Automated Reconfigurable VHDL Generator. In: Proc. of 17th International Conference on Field Programmable Logic and Applications (FPL), Amsterdam, The Netherlands, August 2007, pp. 697–701 (2007)

    Google Scholar 

  9. Meeuws, R.J., Yankova, Y.D., Bertels, K.L.M., Gaydadjiev, G.N., Vassiliadis, S.: A Quantitative Prediction Model for Hardware/Software Partitioning. In: Proc. of 17th International Conference on Field Programmable Logic and Applications (FPL), Amsterdam, The Netherlands, August 2007, pp. 735–739 (2007)

    Google Scholar 

  10. Coussy, P., Morawiec, A.: High-Level Synthesis from Algorithm to Digital Circuit. Springer, Heidelberg (2008)

    Google Scholar 

  11. Chiou, L., Bhunia, S., Roy, K.: Synthesis of Application-Specific Highly Efficient Multi-mode Cores for Embedded Systems. ACM Transaction on Embedded System Computing (TECS) 4(1), 168–188 (2005)

    Article  Google Scholar 

  12. Moreano, N., Borin, E., Souza, C.D., Araujo, G.: Efficient Datapath Merging for Partially Reconfigurable Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems (TCAD) 24(7), 969–980 (2005)

    Article  Google Scholar 

  13. Fazlali, M., Fallah, K.F., Zolghadr, M., Zakerolhosseini, A.: A New Datapath Merging Method for Reconfigurable System. In: Proc. of 5th International Workshop on Applied Reconfigurable Computing (ARC), Karlsruhe Germany, March 2009, pp. 157–168 (2009)

    Google Scholar 

  14. Fazlali, M., Zakerolhosseini, A., Sabeghi, M., Bertels, K.L.M., Gaydadjiev, G.: Datapath Configuration Time Reduction for Run-time Reconfigurable Systems. In: Proc. of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas Nevada, USA, July 2009, pp. 323–327 (2009)

    Google Scholar 

  15. Garey, M., Johnson, D.S.: Computers and Intractability-A Guide to the Theory of NP Completeness. Freeman, San Francisco (1979)

    MATH  Google Scholar 

  16. Ostergard, P.R.J.: A New Algorithm for the Maximum-Weight Clique Problem. Nordic Journal of Computing (NJC) 8(4), 424–436 (2002)

    MathSciNet  Google Scholar 

  17. Lee, C., Potkonjak, M., Mangione, W.S.: Mediabench: a Tool for Evaluating and Synthesizing Multimedia and Communication Systems. In: Proc. of 13th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), California, USA, December 1997, pp. 330–335 (1997)

    Google Scholar 

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Fazlali, M., Zakerolhosseini, A., Gaydadjiev, G. (2010). A Modified Merging Approach for Datapath Configuration Time Reduction. In: Sirisuk, P., Morgan, F., El-Ghazawi, T., Amano, H. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2010. Lecture Notes in Computer Science, vol 5992. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12133-3_29

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  • DOI: https://doi.org/10.1007/978-3-642-12133-3_29

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-12132-6

  • Online ISBN: 978-3-642-12133-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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