Abstract
Using dynamically reconfigurable hardware is useful especially when a high degree of flexibility is demanded and the application requires inherent parallelism to achieve real-time constraints. Depending on various driving conditions different algorithms have to be used for video processing. These different algorithms require different hardware accelerator engines, which are loaded into the AutoVision chip at run-time of the system. The novelties presented in this paper are the determination of the maximum frequency for dynamic partial reconfiguration of Xilinx Virtex-II Pro, Virtex-4 and Virtex-5 devices and a modified overclocked version of the ICAP controller. In addition an online verification approach is presented that can determine configuration errors that might be caused by configuring a device above the specified frequencies. This results in a reconfiguration throughput which is three times higher than the maximum throughput specified by Xilinx.
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Claus, C., Huitl, R., Rausch, J., Stechele, W.: Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. In: Proceedings of FPL 2009, Prague, Czech Republic (2009)
Claus, C., Stechele, W., Herkersdorf, A.: AutoVision - a run-time reconfigurable MPSoC architecture for future driver assistance systems. It-Journal 49(3), 181–187 (2007)
Sun, Z., Bebis, G., Miller, R.: On-road vehicle detection: a review. IEEE Transactions on Pattern Analysis and Machine Intelligence 28(5), 694–711 (2006)
Manet, P., Maufroid, D., Tosi, L., Gailliard, G., Mulertt, O., Ciano, M.D., Legat, J.-D., Aulagnier, D., Gamrat, C., Liberati, R., Barba, V.L., Cuvelier, P., Rousseau, B., Gelineau, P.: An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications. EURASIP Journal on Embedded Systems 2008 (November 2008)
Shelburne, M., Patterson, C., Athanas, P., Jones, M., Martin, B., Fong, R.: Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip. In: Proceedings of FPL 2008, Heidelberg, Germany, pp. 257–262 (2008)
Bomel, P., Crenne, J., Ye, L., Diguet, J.-P., Gogniat, G.: Ultra-Fast Downloading of Partial Bitstreams through Ethernet. In: Sirisuk, P., et al. (eds.) ARC 2010. LNCS, vol. 5992, pp. 72–83. Springer, Heidelberg (2010)
Liu, M., Kuehn, W., Lu, Z., Jantsch, A.: Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration. In: Proceedings of FPL 2009, Prague, Czech Republic (2009)
Claus, C., Laika, A., Jia, L., Stechele, W.: High performance FPGA based optical flow calculation using the census transformation. In: Proceedings of IV 2009, Xi’an, China (2009)
Claus, C., Zhang, B., Stechele, W., Braun, L., Hübner, M., Becker, J.: A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. In: Proceedings of FPL 2008, Heidelberg, Germany, pp. 535–538 (2008)
Hübner, M., Braun, L., Becker, J., Claus, C., Stechele, W.: Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. In: Proceedings of ISVLSI 2007, Porto Alegre, Brazil, pp. 41–46 (2007)
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Claus, C., Ahmed, R., Altenried, F., Stechele, W. (2010). Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems. In: Sirisuk, P., Morgan, F., El-Ghazawi, T., Amano, H. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2010. Lecture Notes in Computer Science, vol 5992. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12133-3_8
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DOI: https://doi.org/10.1007/978-3-642-12133-3_8
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