Abstract
The power consumption of the integrated circuits have become increasingly a central topic of today’s research. The need for low power has caused a major paradigm shift where power dissipation has become as important as performance and area. In this paper the original direct mapped cache of Alpha AXP 21064 processor is modified into set associative and phased set associative caches. The experimental results show that phased set associative cache is more power efficient than set associative cache. These three designs namely direct mapped, set associative and phased set associative caches are modeled using Verilog HDL, simulated in Modelsim and synthesized in Xilinx ISE 10.1. The power estimation and analysis is done using Xilinx XPower Analyser.
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References
Calder, B., Grunwald, D., Emer, J.: Predictive Sequential Associative Cache. In: Proceedings of Second International Symposium on High-Performance Computer Architecture, February 1996, pp. 244–253 (1996)
Chang, J.H., Chao, H., So, K.: Cache design of a sub-micron cmos system/370. In: 14th Annual International Symposium on Computer Architecture, SIGARCH Newsletter, June 1987, pp. 208–213 (1987)
Koji, I., Tohru, I., Kazuaki, M.: Way Predicting Set Associative Cache for High Performance and Low Energy Consumption. In: ISLPED 1999, San Diego, CA, USA (1999)
Hasegawa, A., et al.: SH3: High Code Density, Low Power. IEEE Micro 15(6), 11–19 (1995)
Megalingam, R.K., Deepu, K.B., Joseph, I.P., Vikram, V.: Phased Set Associative Cache Design For Reduced Power Consumption. In: 2nd IEEE ICCSIT 2009, Beijing, China (2009)
Kin, J., Gupta, M., Mangione-Smith, W.H.: The Filter Cache: An Energy Efficient Memory Structure. In: IEEE/ACM International Symposium on Microarchitecture (MICRO-30), pp. 184–193 (1997)
Patterson, D.A., Hennesy, J.L.: Computer Organization and Design, 2nd edn.
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Kannan, M.R., Deepu, K.B., Iype, J.P., Parthasarathy, R., Gautham, P. (2010). Power Consumption Analysis of Direct, Set Associative and Phased Set Associative Cache Organizations in Alpha AXP 21064 Processor. In: Das, V.V., et al. Information Processing and Management. BAIP 2010. Communications in Computer and Information Science, vol 70. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12214-9_20
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DOI: https://doi.org/10.1007/978-3-642-12214-9_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-12213-2
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