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FPGA Implementation of AES Co-processor in Counter Mode

  • Conference paper
Information Processing and Management (BAIP 2010)

Abstract

In many applications strong security and high speed performance is required. For this purpose, DES and AES techniques are usually chosen, but these results in the lowering of security strength and less throughput. This paper presents the design FPGA implementation of AES processor in Counter Mode for 256 bits. In this work, the encryption rate is 52.6124 G bits /sec and memory efficiency is 1.565 with the key length of 256 bits. HDL simulations, verifications and implementations are done on Spartran 3, vertex 2 and vertex E devices.

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Singh, B., Kaur, H., Monga, H. (2010). FPGA Implementation of AES Co-processor in Counter Mode. In: Das, V.V., et al. Information Processing and Management. BAIP 2010. Communications in Computer and Information Science, vol 70. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12214-9_85

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  • DOI: https://doi.org/10.1007/978-3-642-12214-9_85

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-12213-2

  • Online ISBN: 978-3-642-12214-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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