Abstract
In many applications strong security and high speed performance is required. For this purpose, DES and AES techniques are usually chosen, but these results in the lowering of security strength and less throughput. This paper presents the design FPGA implementation of AES processor in Counter Mode for 256 bits. In this work, the encryption rate is 52.6124 G bits /sec and memory efficiency is 1.565 with the key length of 256 bits. HDL simulations, verifications and implementations are done on Spartran 3, vertex 2 and vertex E devices.
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Gaj, K., Chodowiec, P.: FPGA and ASIC Implementations of AES 235-294 FPGA and ASIC Implementations of AES. In: Cryptographic Engineering, pp. 235–294. Springer, US (2008)
Saggese, G.P., Mazzeo, A., Mazzocca, N., Strollo, A.G.M.: An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 292–302. Springer, Heidelberg (2003)
Pramstaller, N., Wolkerstorfer, J.: A universal and efficient AES co-processor for field programmable logic arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 565–574. Springer, Heidelberg (2004)
National Institute of Standards and Technology (NIST), Advanced Encryption Standard, FederaI information Processing Standards Publications 197 (FIPS197) (November 2001)
Canright, D.: A very compact Rijndael S-box, NPSMA (2005)
Liu, J., Wei, B., Cheng, X., Wang, X.: An AES S-Box to Increase Complexity and Cryptographic Analysis. In: 19th IEEE International Conference on Advanced Information Networking and Applications (AINA), Taipei, Taiwan, pp. 724–728 (2005)
Dworkin, M.: Recommendation for Block Cipher Modes of Operation: Methods and Techniques, NIST Special Publication 800-38A (2001)
Fu, Y., Hao, L., Zhang, X., Yang, R.: Design of an Extremely High Performance Counter Mode AES Reconfigurable Processor. In: IEEE Second International Conference on Embedded Software and Systems (2005)
Yang, B., Mishra, S., Karri, R.: High Speed Architecture for Galois / Counter Mode of Operation (GCM), Polytechnic University, Brooklyn, NY (2001)
Diffie, W., Hellman, M.: Privacy and Authentication: An Introduction to Cryptography. IEEE, Los Alamitos ( March 1979)
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Singh, B., Kaur, H., Monga, H. (2010). FPGA Implementation of AES Co-processor in Counter Mode. In: Das, V.V., et al. Information Processing and Management. BAIP 2010. Communications in Computer and Information Science, vol 70. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12214-9_85
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DOI: https://doi.org/10.1007/978-3-642-12214-9_85
Publisher Name: Springer, Berlin, Heidelberg
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