Efficient Partitioning of Static Buses for Processor Arrays of Small Size

Abstract

This paper shows an efficient partitioning of static row/ column buses for tightly coupled 2D mesh-connected processor arrays (mesh for short) of small size. With additional $O({\frac{n}{m}\left(\frac{n}{m}+\log m\right)})$ time slowdown, it enables the mesh of size m ×m with static row/column buses to simulate the mesh of larger size n ×n with reconfigurable row/ column buses (m ≤ n). This means that if a problem can be solved in O(T) time by the mesh of size n ×n with reconfigurable bus, then the same problem can be solved in $O({T\cdot\frac{n}{m}\left(\frac{n}{m}+\log m\right)})$ time on the mesh of smaller size m ×m without reconfigurable function. This time-cost is optimal when the relation n ≥ mlogm holds (e.g., m = n ^1 − ε for ε> 0).