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A Massively Parallel Hardware for Modular Exponentiations Using the m-ary Method

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Algorithms and Architectures for Parallel Processing (ICA3PP 2010)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6082))

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Abstract

Most of cryptographic systems are based on modular exponentiation. It is performed using successive modular multiplications. One way of improving the throughput of a cryptographic system implementation is reducing the number of the required modular multiplications. Existing methods attempt to reduce this number by partitioning the exponent in constant or variable size windows. In this paper, in the purpose of further accelerating the computation of modular exponentiation, a concurrent novel approach is proposed along with hardware implementation of the concurrent m-ary method. We compare the proposed method to the sequential implementation.

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Author information

Authors and Affiliations

  1. Department of Electronics Engineering and Telecommunications, State University of Rio de Janeiro, Brazil

    Marcos Santana Farias, Sérgio de Souza Raposo & Nadia Nedjah

  2. Department of System Engineering and Computation, Engineering Faculty, State University of Rio de Janeiro, Brazil

    Luiza de Macedo Mourelle

Authors
  1. Marcos Santana Farias
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  2. Sérgio de Souza Raposo
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  3. Nadia Nedjah
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  4. Luiza de Macedo Mourelle
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Editor information

Editors and Affiliations

  1. Department of Computer Science and Information Engineering, Chung Hua University, 300, Hsinchu, Taiwan, China

    Ching-Hsien Hsu

  2. Department of Computer Science, St. Francis Xavier University, B2G 2W5, Antigonish, NS, Canada

    Laurence T. Yang

  3. Department of Computer Science ad Engineering, Seoul National University of Technology, 172 Gongreund 2-dong, Nowon-gou, 139-742, Seoul, Korea

    Jong Hyuk Park

  4. Division of Computer Engineering, Mokwon University, 302-729, Daejeon, Korea

    Sang-Soo Yeo

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Santana Farias, M., de Souza Raposo, S., Nedjah, N., de Macedo Mourelle, L. (2010). A Massively Parallel Hardware for Modular Exponentiations Using the m-ary Method. In: Hsu, CH., Yang, L.T., Park, J.H., Yeo, SS. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2010. Lecture Notes in Computer Science, vol 6082. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-13136-3_16

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  • DOI: https://doi.org/10.1007/978-3-642-13136-3_16

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-13135-6

  • Online ISBN: 978-3-642-13136-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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