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Efficient Time-Area Scalable ECC Processor Using μ-Coding Technique

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Arithmetic of Finite Fields (WAIFI 2010)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6087))

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Abstract

The work in this paper discusses the feasibility of a low-resource ECC processor implementation over GF(2m) that supports scalability across a set of standards curves for application in resource constrained environments. A new architecture based on the microcoding technique and targeted to FPGAs is presented for the implementation of a low resource ECC processor design that is scalable to support the 131, 163, 283, 571 bits suite of recommended curves without significant deterioration of the performance. The processor is parameterized for 8, 16, 32-bit data-paths, to quantify the gain in terms of time and area in each case. The implementation results obtained show that the microcode approach results in a lesser area overhead for the ECC point multiplication compared to a full hardware implementation; this makes such approach attractive for numerous applications, where the hardware resources are scarce, as in security in wireless sensor nodes, mobile handsets, and smart cards.

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Hassan, M.N., Benaissa, M. (2010). Efficient Time-Area Scalable ECC Processor Using μ-Coding Technique. In: Hasan, M.A., Helleseth, T. (eds) Arithmetic of Finite Fields. WAIFI 2010. Lecture Notes in Computer Science, vol 6087. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-13797-6_18

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  • DOI: https://doi.org/10.1007/978-3-642-13797-6_18

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-13796-9

  • Online ISBN: 978-3-642-13797-6

  • eBook Packages: Computer ScienceComputer Science (R0)

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