Abstract
This article briefly states the idea behind model-based diagnosis and its application to localizing faults in Verilog programs. Specifically this article outlines how to employ a test suite to further reduce the number of fault candidates. For this purpose, we propose the filtering approach and relate it to the concept of Ackermann constraints. Notably, our empirical results demonstrate that our novel technique considerably increases the diagnosis resolution even under presence of only a couple of test cases.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Ackermann, W.: Solvable Cases of Decision Problems. North Holland, Amsterdam (1954)
Aitken, R.C.: Modeling the unmodelable: Algorithmic fault diagnosis. IEEE Test and Computes 97, 98–103 (1997)
de Kleer, J., Mackworth, A.K., Reiter, R.: Characterizing diagnosis and systems. Artificial Intelligence 56 (1992)
Gordon, M.J.C.: Relating event and trace semantics of hardware description languages. The Computer Journal 45(1), 27–36 (2002)
Holst, S., Wunderlich, H.-J.: Adaptive debug and diagnosis without fault dictionaries. In: ETS ’07: Proceedings of the 12th IEEE European Test Symposium, Washington, DC, USA, pp. 7–12. IEEE Computer Society, Los Alamitos (2007)
Huang, S.-Y., Cheng, K.-T., Chen, K.-C., Lu, J.-Y.J.: Fault-simulation based design error diagnosis for sequential circuits. In: Proceedings of the 35th Design Automation Conference, San Francisco, CA (June 1998)
Peischl, B., Köb, D., Wotawa, F.: Debugging VHDL designs using temporal process instances. In: Chung, P.W.H., Hinde, C.J., Ali, M. (eds.) IEA/AIE 2003. LNCS (LNAI), vol. 2718, pp. 402–415. Springer, Heidelberg (2003)
Peischl, B., Riaz, N., Wotawa, F.: Advances in automated source-level debugging of verilog designs. Studies in Computational Intelligence. Springer, Heidelberg (2008)
Peischl, B., Riaz, N., Wotawa, F.: Model-based reasoning with multiple test cases and its application to debugging. In: 19th International Workshop on Principles of Diagnosis (September 2008)
Peischl, B., Riaz, N., Wotawa, F.: Test patterns for verilog design error localization. To appear in the Proceedings of the TAIC PART 2009, Windsor, UK (September 2009)
Peischl, B., Wotawa, F.: Automated source-level error localization in hardware designs. IEEE Design and Test 23(1), 8–19 (2006)
Raiman, O., de Kleer, J., Saraswat, V., Shirley, M.: Characterizing non-intermittent faults. In: Proceedings AAAI, Anaheim, July 1991, pp. 849–854. Morgan Kaufmann, San Francisco (1991)
Reiter, R.: A theory of diagnosis from first principles. Artificial Intelligence 32(1), 57–95 (1987)
Riaz, N.: Source-Level Debugging of Verilog Designs. PhD thesis, Technische Universität Graz (November 2008)
Rousset, A., Bosio, A., Girard, P., Landrault, C., Pravossoudovitch, S., Virazel, A.: Derric: A tool for unified logic diagnosis. In: ETS ’07: Proceedings of the 12th IEEE European Test Symposium, Washington, DC, USA, pp. 13–20. IEEE Computer Society, Los Alamitos (2007)
Staber, S., Fey, G., Bloem, R., Drechsler, R.: Automatic fault localization for property checking. In: Second International Haifa Verification Conference, Haifa, October 2006, pp. 50–64 (2006)
Wang, L.-T., Hoover, N.E., Porter, E.H., Zasio, J.J.: Ssim: a software levelized compiled-code simulator. In: 24th ACM/IEEE conference proceedings on Design automation conference, pp. 2–8. ACM Press, New York (1987)
Wotawa, F.: Applying Model-Based Diagnosis to Software Debugging of Concurrent and Sequential Imperative Programming Languages. PhD thesis, Technische Universität Wien (1996)
Wotawa, F.: Debugging VHDL Designs using Model-Based Reasoning. Artificial Intelligence in Engineering 14(4), 331–351 (2000)
Wotawa, F.: Debugging hardware designs using a value-based Model. Applied Intelligence 16(1), 71–92 (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Peischl, B., Riaz, N., Wotawa, F. (2010). Employing Test Suites for Verilog Fault Localization. In: Meseguer, P., Mandow, L., Gasca, R.M. (eds) Current Topics in Artificial Intelligence. CAEPIA 2009. Lecture Notes in Computer Science(), vol 5988. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14264-2_1
Download citation
DOI: https://doi.org/10.1007/978-3-642-14264-2_1
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-14263-5
Online ISBN: 978-3-642-14264-2
eBook Packages: Computer ScienceComputer Science (R0)