Abstract
Semiconductor memories are considered one of the most important aspects of modern microelectronics. Memories are the most important universal components in SoC (System on Chip) today. Almost all SoC’s contain some type of embedded memories, such as ROM, RAM, DRAM and flash memory. Testing them becomes a challenge as these devices become more complex. The modeling and simulation of Memory BIST is presented in this paper. The architecture is implemented using Hardware Description Language and an area overhead is analyzed. The LR algorithm is implemented on to test the SRAM faults like stuck at faults, inversion coupling faults, linked faults etc.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
International Technology Roadmap for Semiconductors, ITRS (2007), http://public.itrs.net
Hamdioui, S., Gaydadjiev, G., van de Goor, A.J.: The state-of-art and future trends in testing embedded memories. In: International Workshop on Memory Technology, Design and Testing, pp. 54–59 (2004)
Grout Ian, A.: Integrated circuit test engineering: modern techniques. Springer, Berlin (2006)
Riedel, M., Rajski, J.: Fault coverage analysis of RAM test algorithms. In: Proceedings of the 13th IEEE VLSI Test Symposium, pp. 227–234 (1995)
Harutunyan, G., Vardanian, V.A., Zorian, Y.: Minimal March Tests for Unlinked Static Faults in Random Access Memories. In: Proceeding of VLSI Test Symposium, pp. 53–59 (2005)
Benso, A., Bosio, A., Di Carlo, S., Di Natale, G., Prinetto, P.: March AB, March AB1: New March Tests for Unlinked Dynamic Memory Faults. In: Proceeding of International Test Conference, pp. 841–848 (2005)
Hamdioui, S., Al-Ars, Z., van de Goor, A.J.: Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Transactions on Computers 55(12), 1630–1639 (2006)
Harutunyan, G., Vardanian, V.A., Zorian, Y.: Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. In: Proceeding. of VLSI Test Symposium, pp. 120–127 (2006)
Hamdioui, S., van de Goor, A.J., Rodgers, M.: March SS: A Test or All Static Simple RAM Faults. In: Proc. of MTDT, pp. 95–100 (2002)
Haron, N.Z., Yunus, S.A.M., Aziz, A.S.A.: Modeling and simulation of microcode Memory Built In Self Test architecture for embedded memories. In: International Symposium on Communications and Information Technologies, pp. 136–139 (2007)
Lu, J.-M., Wu, C.-W.: Cost and benefit models for logic and memory BIST Design. In: Proceedings of Automation and Test in Europe Conference, pp. 27–30 (2000)
Cheng Allen, C.: Comprehensive Study on designing Memory BIST: Algorithms, implementations and Trade-offs. In: EECS 579, 48109–2122. University of Michigan, Ann Arbor (2002)
Zarrineh, K., Upadhyaya, S.J.: On programmable memory built-in self test architectures, Design, Automation and Test. In: Proceedings Europe Conference and Exhibition, pp. 708–713 (1999)
Al-Ars, Z., van de Goor, A.J.: Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs. In: Proceedings of DATE, pp. 401–406 (2001)
Van de Goor, A.J., Gayadadjiev, G.N., Yarmolik, V.N., Mikitjuk, V.G.: March LR: A Test for Realistic Linked Faults. In: 16th IEEE VLSI ISE 9.2i Software Test Symposium, pp. 272–280 (1996)
Rochit, R.: System-on-a-Chip: Design and Test, pp. 155–177. Artech house. Inc., Norwood (2000)
Xilinx Manuals, http://www.xilinx.com/itp/xilinx92/books/manuals.pdf
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Singh, B., Narang, S.B., Khosla, A. (2010). Modeling and Simulation of Efficient March Algorithm for Memory Testing. In: Ranka, S., et al. Contemporary Computing. IC3 2010. Communications in Computer and Information Science, vol 95. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14825-5_9
Download citation
DOI: https://doi.org/10.1007/978-3-642-14825-5_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-14824-8
Online ISBN: 978-3-642-14825-5
eBook Packages: Computer ScienceComputer Science (R0)