Abstract
In order to obtain the balance of the decoding rate and the hardware consumption, a new method to design LDPC decoder is proposed, which is a communicating sequential process model intended for streams-oriented and mixed hardware/software applications. For the characteristics of the decoding algorithm, this method is based on an up-to-date parallel technique from Impulse C programming to FPGA hardware implementation, which is more efficient than the traditional HDL method. A decoder for a family of (3,6) LDPC Codes with a code rate of 0.5 and a block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000. By performing maximum 10 decoding iterations, the decoder can achieve a maximum bit throughput of 10Mbps.
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Zhang, P., Tao, Z., Wang, Y., Zhou, C. (2010). An Impulse C Application in the LDPC Decoding Algorithm. In: Huang, DS., McGinnity, M., Heutte, L., Zhang, XP. (eds) Advanced Intelligent Computing Theories and Applications. ICIC 2010. Communications in Computer and Information Science, vol 93. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14831-6_60
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DOI: https://doi.org/10.1007/978-3-642-14831-6_60
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-14830-9
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