Real-Time Architecture for Inter-layer Prediction of H.264/SVC

Abstract

In this paper, an efficient architecture for Inter-layer prediction of H.264/SVC is proposed. The proposed architecture is based on a two-layer model with QCIF and CIF size for base layer and enhancement layer, respectively. In the proposed architecture, the motion vector prediction mode is not concerned due to its limited coding efficiency. Only the Intra prediction mode and residual prediction mode in inter-layer prediction are supported. Furthermore, on the basis of our simulation results, the residual prediction mode is rarely selected. Using an efficient mode selection algorithm which is proposed by our previous work, the complexity of residual prediction is significantly reduced. Therefore, to realize real-time processing with low cost hardware, the proposed architecture makes use of a single-core coding engine. The basic coding core is the same as the traditional H.264/AVC with a novel supplemental up-sampling core. Using this coding core, the macroblock encoding is performed for base layer and enhancement layer alternatively. The proposed up-sampling module is described by Verilog-HDL and synthesis results show that the gate counts are 16,121 and the maximum working frequency is 141MHz.