Abstract
A new CMOS voltage-mode Four-quadrant analog Multiplier is proposed and analyzed. By applying inputs signals to set of complementary diode pair connection & to that of voltage difference circuit. The circuit is formed by cascading the complementary diode pair connection with the voltage difference circuit. Based on the proposed multiplier circuit, a low voltage high performance CMOS four quadrant analog multiplier is designed and fabricated by using 0.35micron technology. The measured 3dB bandwidth is 15 MHz Simple structure, low-voltage, low power, and high performance makes the proposed multiplier quite feasible in many applications.
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Tijare, A., Dakhole, P. (2010). VLSI Design of Four Quadrant Analog Voltage-Mode Multiplier and Its Application. In: Das, V.V., Vijaykumar, R. (eds) Information and Communication Technologies. ICT 2010. Communications in Computer and Information Science, vol 101. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15766-0_8
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DOI: https://doi.org/10.1007/978-3-642-15766-0_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-15765-3
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