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Method for Formal Verification of Soft-Error Tolerance Mechanisms in Pipelined Microprocessors

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Formal Methods and Software Engineering (ICFEM 2010)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 6447))

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Abstract

We present techniques for design and formal verification of both safety and liveness of pipelined/superscalar/VLIW processors with built-in mechanisms for soft-error tolerance. The formal verification is done with the highly automatic method of Correspondence Checking by exploiting the property of Positive Equality and efficient translations of the correctness conditions to equivalent Boolean formulas that are evaluated with SAT solvers. Soft errors are caused by radiation and cross talk between devices or wires on the chip, and will become increasingly frequent with the decreasing transistor sizes in future technologies. Soft errors can cause catastrophic failures in safety-critical applications, such as space, avionics, weapons systems, automotive, and medical devices. Thus, the need to design and efficiently formally verify pipelined microprocessors with mechanisms for soft-error tolerance.

This research was partially supported by NASA under contract NNX10CC60P.

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Authors and Affiliations

  1. Aries Design Automation, US

    Miroslav N. Velev & Ping Gao

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  1. Miroslav N. Velev
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  2. Ping Gao
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  1. School of Computing, Computer Science Dept, National University of Singapore, 13 Computing Drive, 117417, Singapore, Singapore

    Jin Song Dong

  2. Software Engineering Institute, East China Normal University, 3663 Zhongshan Road (North), 200062, Shanghai, China

    Huibiao Zhu

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Velev, M.N., Gao, P. (2010). Method for Formal Verification of Soft-Error Tolerance Mechanisms in Pipelined Microprocessors. In: Dong, J.S., Zhu, H. (eds) Formal Methods and Software Engineering. ICFEM 2010. Lecture Notes in Computer Science, vol 6447. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-16901-4_24

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  • DOI: https://doi.org/10.1007/978-3-642-16901-4_24

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