Abstract
This paper presents a security design for embedded systems that have a secure on-chip computing environment and an insecure off-chip memory. The design protects the confidentiality and integrity of data at a low cost on performance and memory consumption. We implemented the design based on the SimpleScalar simulation software. Our simulation on a set of benchmarks shows that very little overhead is incurred for on-chip memory, and the average overheads on performance and off-chip memory, are only 7.6% and 6.25%, respectively.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Gelbart, O., Leontie, E., Narahari, B., Simha, R.: A compiler-hardware approach to software protection for embedded systems. Computers and Electrical Engineering, 315–328 (2009)
Ravi, S., Raghunathan, A., Chakradhar, S.: Tamper resistance mechanisms for secure embedded systems. In: 17th International Conference on VLSI Design (2004)
Best, R.M.: Prevent software piracy with crypto-microprocessors. In: IEEE Computer Society International Conference (1980)
Dallas Semiconductor (2008), http://www.maximic.com/Microcontroller.cfm
Blum, M., Evans, W., Gemmell, P., Kannan, S., Naor, M.: Checking the correctness of memories. In: 32nd Annual Symposium on Foundations of Computer Science (1991)
Lie, D., Chandramohan, T., Mitchell, M., Lincoln, P., Boneh, D., Mitchell, J., Horowitz, M.: Architectural support for copy and tamper resistant software. In: 9th Internatinal Conference Architectural Support for Programming Languages and Operating Systems, ASPLOS-IX (2000)
Lie, D., Thekkath, C.A., Horowitz, M.: Implementing an untrusted operating system on trusted hardware. In: 19th ACM Symposium on Operating System Principles (2003)
Suh, G.E., Clarke, D., Gasend, B., van Dijk, M., Devadas, S.: AEGIS:architecure for tamper-evident and tamper-resistant processing. In: International Conference on SuperComputing (2003)
Suh, G.E., óDonnell, C.W., Sachdev, I., Devadas, S.: Design and implementation of the AEGIS single-chip secure processor using physical random functions. In: 32nd Interntional Symposium on Computer Architecture, ISCA (2005)
Suh, G.E., óDonnell, C.W., Sachdev, I., Devadas, S.: AEGIS: A single-chip secure processor. IEEE Design and Test of Computers, 467–477 (2007)
Duc, G., Keryell, R.: Cryptopage: An efficient secure architecture with memory encryption, integrity and information leakage protection. In: 22nd Annual Computer Security Applications Conference, ACSAC 2006 (2006)
Elbaz, R., Champagne, D., Lee, R.B., Torres, L.: Tec-tree: a low-cost, parallelizable tree for efficient defense against memory replay attacks. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 289–302. Springer, Heidelberg (2007)
Bellare, M., Namprempre, C.: Authenticated encryption: Relations among notions and analysis of the generic composition paradigm. Journal of Cryptology 21(4), 469–491 (2008)
Rogaway, P., Bellare, M., Black, J., Krovetz, T.: OCB: a block-cipher mode of operation for efficient authenticated encryption. In: ACM conference on Computer and communications Security (2001)
Austin, T.M., Burger, D.B.: The simplescalar tool set, version 3.0. Technical report, University of Wisconsin-madision (1997)
Helion Technology Datasheet: high performance AES (Rijndael) cores for Xilinx FPGAs (2008), http://www.heliontech.com
Henning, J.L.: SPEC CPU 2000: Measuing CPU performance in the new millennium. IEEE Computers (2000)
Guthaus, M.R., Ringenberg, J.S.: Mibench: a free, commercially representiative embedded benchmark suite. In: IEEE 4th Annual Workshop on Workload Characterization (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Hong, M., Guo, H. (2010). FEDTIC: A Security Design for Embedded Systems with Insecure External Memory. In: Kim, Th., Lee, Yh., Kang, BH., Ślęzak, D. (eds) Future Generation Information Technology. FGIT 2010. Lecture Notes in Computer Science, vol 6485. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17569-5_36
Download citation
DOI: https://doi.org/10.1007/978-3-642-17569-5_36
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-17568-8
Online ISBN: 978-3-642-17569-5
eBook Packages: Computer ScienceComputer Science (R0)