Abstract
In this paper, we propose a fully parallel, high-speed bit-plane coding (BPC) hardware architecture for the embedded block coding with optimized truncation (EBCOT) module in JPEG 2000. The BPC is the most complicated and critical part in design and implementation of the EBCOT. In addition, the BPC consumes most of the computation time in the EBCOT. Thus, a high-speed BPC hardware architecutre is strongly required for the real-time high-resolustion JPEG 2000 systems. To increase BPC throughput, the proposed hardware architecture performs BPC coding in all the bit planes in parallel through the proposed significance look-ahead methods. Experimental results show that the proposed architecture increases BPC throughput twice when compared with the previously proposed BPC architectures.
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Woo, DH., Bae, KR., Son, HS., Ok, SH., Lee, Y.H., Moon, B. (2010). A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000. In: Kim, Th., Vasilakos, T., Sakurai, K., Xiao, Y., Zhao, G., Ślęzak, D. (eds) Communication and Networking. FGCN 2010. Communications in Computer and Information Science, vol 120. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17604-3_42
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DOI: https://doi.org/10.1007/978-3-642-17604-3_42
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-17603-6
Online ISBN: 978-3-642-17604-3
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