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Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers

  • Conference proceedings
  • © 2011

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Editors:
  1. René Leuken

    1. EEMCS/MECE/CAS, Delft University of Technology, Delft, The Netherlands

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  2. Gilles Sicard

    1. TIMA Laboratory, Grenoble, France

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 6448)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

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Conference proceedings info: PATMOS 2010.

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About this book

This book constitutes the refereed proceedings of the 20th International Conference on Integrated Circuit and System Design, PATMOS 2010, held in Grenoble, France, in September 2010. The 24 revised full papers presented and the 9 extended abstracts were carefully reviewed and are organized in topical sections on design flows; circuit techniques; low power circuits; self-timed circuits; process variation; high-level modeling of poweraware heterogeneous designs in SystemC-AMS; and minalogic.

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Table of contents (32 papers)

  1. Front Matter

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  2. Session 1: Design Flows

    1. A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC

      • Tanguy Sassolas, Nicolas Ventroux, Nassima Boudouani, Guillaume Blanc
      Pages 1-10

    2. An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software

      • Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, Josef Haid
      Pages 11-20

    3. System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk

      • Martin Gag, Tim Wegner, Dirk Timmermann
      Pages 21-30

    4. Residue Arithmetic for Designing Low-Power Multiply-Add Units

      • Ioannis Kouretas, Vassilis Paliouras
      Pages 31-40

  3. Session 2: Circuit Techniques 1

    1. An On-Chip Flip-Flop Characterization Circuit

      • Abhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi
      Pages 41-50

    2. A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion

      • Lida Ramezani
      Pages 51-61

    3. Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits

      • Massimo Alioto, Elio Consoli, Gaetano Palumbo
      Pages 62-72

    4. A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework

      • Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Pekmestzi
      Pages 73-83

  4. Session 3: Low Power Circuits

    1. An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs

      • Cristiano Lazzari, Jorge Fernandes, Paulo Flores, José Monteiro
      Pages 84-93

    2. On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS

      • Pascal Vivet, Edith Beigne, Hugo Lebreton, Nacer-Eddine Zergainoh
      Pages 94-104

    3. Self-Timed SRAM for Energy Harvesting Systems

      • Abdullah Baz, Delong Shang, Fei Xia, Alex Yakovlev
      Pages 105-115

    4. L1 Data Cache Power Reduction Using a Forwarding Predictor

      • P. Carazo, R. Apolloni, F. Castro, D. Chaver, L. Pinuel, F. Tirado
      Pages 116-125

  5. Session 4: Self-Timed Circuits

    1. Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations

      • Mohsen Raji, Alireza Tajary, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi
      Pages 126-136

    2. Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case

      • Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet
      Pages 137-149

    3. Hermes-A – An Asynchronous NoC Router with Distributed Routing

      • Julian Pontes, Matheus Moreira, Fernando Moraes, Ney Calazans
      Pages 150-159

    4. Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip

      • Alberto Garcia-Ortiz, Leandro S. Indrusiak
      Pages 160-169

  6. Session 5: Process Variation

    1. Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing

      • Bahman Kheradmand-Boroujeni, Christian Piguet, Yusuf Leblebici
      Pages 170-179

    2. Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis

      • Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
      Pages 180-189

    3. Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations

      • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs
      Pages 190-199
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Other volumes

  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

Editors and Affiliations

  • EEMCS/MECE/CAS, Delft University of Technology, Delft, The Netherlands

    René Leuken

  • TIMA Laboratory, Grenoble, France

    Gilles Sicard

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