Abstract
With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core DVFS is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Bhunia, S., Datta, A., Banerjee, N., Roy, K.: GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. IEEE Transactions on Computer, Special Issue on low-Power Design (99), 752–766 (June 2005)
Sylvain, M., Vivet, P., Renaudin, M.: A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. In: Azémard, N., Svensson, L. (eds.) PATMOS 2007. LNCS, vol. 4644, pp. 556–565. Springer, Heidelberg (2007)
Truonga, D., et al.: A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling. In: Proc. Symposium on VLSI Circuits (June 2008)
Mishra, R., Rastogi, N., Zhu, D., Mosse, D., Melhem, R.: Energy aware scheduling for distributed real-time systems. In: Proc. of Parallel and Distributed Processing Symposium (April 2003)
Watanabe, R., Kondo, M., Imai, M., Nakamura, H., Nanya, T.: Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC Design. In: DATE 2007 (2007)
Xian, C., Lu, Y., Li, Z.: Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution Time. In: DAC 2007, pp. 664–669 (2007)
Grosse, P., Durand, Y., Feautrier, P.: Methods for Power Optimization in SoC-based Data Flow Systems. ACM Transactions On Design Automation of Electronic Systems (TODAES 2009) 14(3), Article No. 38 (2009)
Niyogi, K., Marculescu, D.: Speed and voltage selection for GALS systems based on voltage/frequency islands. In: Proceedings of, ASP-DAC 2005 (2005)
Puschini, D., Clermidy, F., Benoit, P., Sassatelli, G., Torres, L.: Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory. In: Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, pp. 375–380 (2008)
Alimonda, A., Acquaviva, A., Carta, S., Pisano, A.: A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Processing in MPSoCs Design. In: Proceedings of Design Automation and Test in Europe, DATE 2006 (2006)
Maxiaguine, A., Chakraborty, S., Thiele, L.: DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs. In: 3rd International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, pp. 111–116 (2005)
Beigné, E., Clermidy, F., Miermont, S., Vivet, P.: Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. In: Proceedings of NOCS 2008 (2008)
Beigné, E., et al.: An Asynchronous Power Aware and Adaptive NoC based Circuit. IEEE Journal Of Solid State Circuits 44, 1167–1177 (2009)
Clermidy, F., et al.: A 477mW NoC-Based Digital Baseband for MIMO 4G SDR. In: Proceedings of IEEE International Solid-State Circuits Conference, ISSCC 2010 (2010)
Lebreton, H., Vivet, P.: Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. In: Proc. of Int. Symposium on VLSI, ISVLSI 2008, pp. 463–466 (2008)
Soongsoo, L., Sakurai, T.: Run-time Voltage Hopping for Low-Power Real-time Systems. In: Proc. of 37th Design Automation Conference, DAC 2000, pp. 806–809 (June 2000)
Yan, Z., Zhijian, L., Lach, J., Skadron, K., Stan, M.R.: Optimal procrastinating voltage scheduling for hard real-time systems. In: DAC 2005, pp. 905–909 (June 2005)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Vivet, P., Beigne, E., Lebreton, H., Zergainoh, NE. (2011). On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_10
Download citation
DOI: https://doi.org/10.1007/978-3-642-17752-1_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-17751-4
Online ISBN: 978-3-642-17752-1
eBook Packages: Computer ScienceComputer Science (R0)