Abstract
Increasing levels of process variability in deep sub micron era has become a critical concern for performance and power constraint designs. This paper introduces a framework for the statistical leakage power minimization of template-based asynchronous circuits considering process variation. We propose a statistical Dual-Vt assignment of asynchronous circuits that considers both the variability in performance and leakage power consumption of a circuit. The utilized circuit model is an extended Timed Petri-Net named Variant-Timed Petri-Net which captures the dynamic behavior of the circuit with statistical delay and leakage power values. We applied a genetic algorithm that uses a 2-dimensional graph to calculate the fitness to each threshold voltage assignment. Experimental results show that using this statistically aware optimization, leakage power can be reduced by 40.5% and 54.4% for the mean and the variance values.
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Raji, M., Tajary, A., Ghavami, B., Pedram, H., Zarandi, H.R. (2011). Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_13
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DOI: https://doi.org/10.1007/978-3-642-17752-1_13
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