Abstract
Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.
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Garcia-Ortiz, A., Indrusiak, L.S. (2011). Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_16
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DOI: https://doi.org/10.1007/978-3-642-17752-1_16
Publisher Name: Springer, Berlin, Heidelberg
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