Abstract
This paper presents a novel method for generating current source models (CSMs) for logic cells that efficiently captures the influences of parameter variation and supply voltage drops. The characterization exploits topological information from the transistor netlist resulting in typically 80x faster CSM library generation. The parametric CSMs have been integrated into a commercial FastSPICE simulator to further accelerate path-based timing analysis with transistor level accuracy.Without loss of accuracy, simulation times were reduced by 4x to 98x.
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Knoth, C., Eichwald, I., Nordholz, P., Schlichtmann, U. (2011). White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_20
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DOI: https://doi.org/10.1007/978-3-642-17752-1_20
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