Abstract
In this paper, an extensive comparison of flip-flop (FF) topologies for high-speed applications is carried out in a 65-nm CMOS technology. This work goes beyond previous analyses in that traditional rankings do not include layout parasitics, which strongly affect both speed and energy and lead to drastic changes in the optimum transistor sizing. For this reason, in this work layout parasitics are included in the circuit design loop by adopting a novel strategy. The obtained results show that the energy efficiency and the performance of FFs is mainly determined by the regularity of their topology and layout. Finally, the area-delay tradeoff is also analyzed for the first time.
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Alioto, M., Consoli, E., Palumbo, G. (2011). Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_7
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DOI: https://doi.org/10.1007/978-3-642-17752-1_7
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