Abstract
The shrinking of interconnect width and thickness, due to technology scaling, along with the integration of low-k dielectrics, reveal novel reliability wear-out mechanisms, progressively affecting the performance of complex systems. These phenomena progressively deteriorate the electrical characteristics and therefore the delay of interconnects, leading to violations in timing-critical paths. This work estimates the timing impact of Time-Dependent Dielectric Breakdown (TDDB) between wires of the same layer, considering temperature variations. The proposed framework is evaluated on a Leon3 MP-SoC design, implemented at a 45nm CMOS technology. The results evaluate the system’s performance drift due to TDDB, considering different physical implementation scenarios.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
ITRS 2005 public reports (2005), http://public.itrs.net
Chen, F., et al.: Critical low-k reliability issues for advanced CMOS technologies. In: Proc. of the 2009 IRPS Symposium, Montreal, Canada, May 26-30, pp. 464–475 (2009)
Nitta, S., et al.: Copper BEOL interconnects for silicon CMOS logic technology. In: Davis, J.A., Meindl, J.D. (eds.) Interconnect Technology and Design for Gigascale Integration. Springer, Heidelberg (2003)
Gonella, R.: Key reliability issues for copper integration in damascene architecture. Journal of Microelectronic Engineering 55(1-4), 245–255 (2001)
Tan, T.L., Gan, C.L., Du, A.Y., Cheng, C.K., Gambino, J.P.: Dielectric degradation mechanism for copper interconnects capped with CoWP. Applied Physics, Letter. 92, 201916 (2008)
Takeda, K.-i., Ryuzaki, D., Mine, T., Hinode, K., Yoneyama, R.: Copper-induced dielectric breakdown in silicon oxide deposited by plasma-enhanced chemical vapor deposition using trimethoxysilane. Journal of Applied Physics 94(2572) (2003)
Chen, F., et al.: Line-edge roughness and spacing effect on low-k TDDB characteristics. In: Proceedings of the 2008 International Reliability Physics Symposium (IRPS), April 27-May 1, pp. 132–138 (2008)
Chen, F., Shinosky, M.: Addressing Cu/Low-k Dielectric TDDB Reliability Challenges for Advanced CMOS Technologies. IEEE Transactions on Electron Devices 56(1), 2–12 (2009)
Li, Y.: Low-k dielectric reliability in copper interconnects, PhD Dissertation, Katholieke Universiteit Leuven (2007)
Guo, J., et al.: A Tool Flow for Predicting System-Level Timing Failures due to Interconnect Reliability Degradation. In: Proc. of the 2008 GLSVLSI International Symposium, Orlando, Florida, USA, May 4-6, pp. 291–296 (2008)
Guo, J., et al.: The Analysis of system level timing failures due to interconnect reliability degradation. IEEE Transactions on Device and Material Reliability (2009)
Huang, W., Ghosh, S., Velusamy, S., Sankaranarayanan, K., Skadron, K., Stan, M.R., Brown, C.L.: HotSpot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Transactions on VLSI Systems 14(5) (May 2006)
Cadence SoC Encounter Database Access command reference, http://www.cadence.com
Aeroflex Gaisler Research, http://www.gaisler.com
Mentor Graphics ModelSim, http://www.model.com
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Bekiaris, D., Papanikolaou, A., Papameletis, C., Soudris, D., Economakos, G., Pekmestzi, K. (2011). A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_8
Download citation
DOI: https://doi.org/10.1007/978-3-642-17752-1_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-17751-4
Online ISBN: 978-3-642-17752-1
eBook Packages: Computer ScienceComputer Science (R0)