Abstract
The shrinking of interconnect width and thickness, due to technology scaling, along with the integration of low-k dielectrics, reveal novel reliability wear-out mechanisms, progressively affecting the performance of complex systems. These phenomena progressively deteriorate the electrical characteristics and therefore the delay of interconnects, leading to violations in timing-critical paths. This work estimates the timing impact of Time-Dependent Dielectric Breakdown (TDDB) between wires of the same layer, considering temperature variations. The proposed framework is evaluated on a Leon3 MP-SoC design, implemented at a 45nm CMOS technology. The results evaluate the system’s performance drift due to TDDB, considering different physical implementation scenarios.
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Bekiaris, D., Papanikolaou, A., Papameletis, C., Soudris, D., Economakos, G., Pekmestzi, K. (2011). A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_8
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DOI: https://doi.org/10.1007/978-3-642-17752-1_8
Publisher Name: Springer, Berlin, Heidelberg
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