Abstract
In this paper we discuss the development of two emulation platforms for transactional memory systems on a single Field Programmable Gate Array (FPGA). We introduce two systems, integrating only off-the-shelf components, that respectively use a centralized and a distributed approach, presenting their hardware and software design. We analyze and compare these two architectures to a lock based multiprocessor prototype, discussing the trade-offs in terms of design complexity, performance and scalability.
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References
Research Accelerator for Multiple Processors (RAMP), http://ramp.eecs.berkeley.edu/
Dragojevic, V.G.A., Felber, P., Guerraoui, R.: Why STM can be more than a Research Toy. Technical report, EPFL (2009)
Arnold, J.M., Buell, D.A., Davis, E.G.: Splash 2. In: SPAA 1992: ACM Symposium on Parallel Algorithms and Architectures, pp. 316–322 (1992)
Baugh, L., Neelakantam, N., Zilles, C.: Using hardware memory protection to build a high-performance, strongly-atomic hybrid transactional memory. SIGARCH Comput. Archit. News 36(3), 115–126 (2008)
Grinberg, S., Weiss, S.: Investigation of transactional memory using fpgas. In: IEEE 24th Convention of Electrical and Electronics Engineers in Israel, pp. 119–122 (2006)
Hammond, L., Carlstrom, B.D., Wong, V., Chen, M., Kozyrakis, C., Olukotun, K.: Transactional coherence and consistency: Simplifying parallel hardware and software. IEEE Micro 24, 92–103 (2004)
Herlihy, M., Moss, J.E.B.: Transactional memory: architectural support for lock-free data structures. SIGARCH Comput. Archit. News 21(2), 289–300 (1993)
Kachris, C., Kulkarni, C.: Configurable transactional memory. In: FCCM 2007: IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 65–72 (2007)
Njoroge, N., Casper, J., Wee, S., Teslyar, Y., Ge, D., Kozyrakis, C., Olukotun, K.: Atlas: a chip-multiprocessor with transactional memory support. In: DATE 2007: Design, Automation and Test in Europe, pp. 3–8 (2007)
Rajwar, R., Goodman, J.R.: Transactional lock-free execution of lock-based programs. In: ASPLOS-X: Architectural Support for Programming Languages and Operating Systems, pp. 5–17 (2002)
Shavit, N., Touitou, D.: Software transactional memory. In: PODC 1995: ACM Symposium on Principles of Distributed Computing, pp. 204–213 (1995)
Tumeo, A., Pilato, C., Palermo, G., Ferrandi, F., Sciuto, D.: HW/SW methodologies for synchronization in FPGA multiprocessors. In: FPGA 2009: ACM/SIGDA Symposium on Field Programmable Gate Arrays, pp. 265–268 (2009)
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Pusceddu, M., Ceccolini, S., Tumeo, A., Palermo, G., Sciuto, D. (2011). Emulating Transactional Memory on FPGA Multiprocessors. In: Berekovic, M., Fornaciari, W., Brinkschulte, U., Silvano, C. (eds) Architecture of Computing Systems - ARCS 2011. ARCS 2011. Lecture Notes in Computer Science, vol 6566. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19137-4_7
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DOI: https://doi.org/10.1007/978-3-642-19137-4_7
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