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MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays

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Reconfigurable Computing: Architectures, Tools and Applications (ARC 2011)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6578))

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Abstract

Optically reconfigurable gate array (ORGAs) were developed to realize next-generation large-virtual gate count programmable VLSIs. An ORGA consists of an ORGA-VLSI, a holographic memory, and a laser array, which is used for addressing the holographic memory. Since many configuration contexts can be stored on a volume-type holographic memory, the corresponding number of lasers must be implemented on an ORGA. However, a laser array with numerous lasers is always expensive. Therefore, to accommodate numerous configuration contexts with fewer lasers, this paper presents a novel method using an interleaving read operation of a holographic memory for ORGAs. This method can provide an addressing capability of a billion configuration contexts along with a nanosecond-order high-speed configuration capability.

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References

  1. Altera Corporation, Altera Devices, http://www.altera.com

  2. Xilinx Inc., Xilinx Product Data Sheets, http://www.xilinx.com

  3. Lattice Semiconductor Corporation, LatticeECP and EC Family Data Sheet (2005), http://www.latticesemi.co.jp/products

  4. Mumbru, J., Panotopoulos, G., Psaltis, D., An, X., Mok, F., Ay, S., Barna, S., Fossum, E.: Optically Programmable Gate Array. In: SPIE of Optics in Computing 2000, vol. 4089, pp. 763–771 (2000)

    Google Scholar 

  5. Mumbru, J., Zhou, G., An, X., Liu, W., Panotopoulos, G., Mok, F., Psaltis, D.: Optical memory for computing and information processing. In: SPIE on Algorithms, Devices, and Systems for Optical Information Processing III, vol. 3804, pp. 14–24 (1999)

    Google Scholar 

  6. Mumbru, J., Zhou, G., Ay, S., An, X., Panotopoulos, G., Mok, F., Psaltis, D.: Optically Reconfigurable Processors. In: SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing, vol. 74, pp. 265–288 (1999)

    Google Scholar 

  7. Yamaguchi, N., Watanabe, M.: Liquid crystal holographic configurations for ORGAs. Applied Optics 47(28), 4692–4700 (2008)

    Article  Google Scholar 

  8. Seto, D., Watanabe, M.: A dynamic optically reconfigurable gate array - perfect emulation. IEEE Journal of Quantum Electronics 44(5), 493–500 (2008)

    Article  Google Scholar 

  9. Watanabe, M., Kobayashi, F.: Dynamic Optically Reconfigurable Gate Array. Japanese Journal of Applied Physics 45(4B), 3510–3515 (2006)

    Article  Google Scholar 

  10. Nakajima, M., Watanabe, M.: A four-context optically differential reconfigurable gate array. IEEE/OSA Journal of Lightwave Technology 27(20), 4460–4470 (2009)

    Article  Google Scholar 

  11. Nakajima, M., Watanabe, M.: A 100-Context Optically Reconfigurable Gate Array. In: IEEE International Symposium on Circuits and Systems, pp. 2884–2887 (2010)

    Google Scholar 

  12. Ogiwara, A., Watanabe, M., Mabuchi, T., Kobayashi, F.: Formation of holographic memory for defect tolerance in optically reconfigurable gate arrays. Applied Optics 49(22), 4255–4261 (2010)

    Article  Google Scholar 

  13. Texas Instruments, DLP, http://www.ti.com/

  14. Texas Instruments, Discovery 4000, http://www.ti.com/

  15. Morita, H., Watanabe, M.: Microelectromechanical Configuration of an Optically Reconfigurable Gate Array. IEEE Journal of Quantum Electronics 46(9), 1288–1294 (2010)

    Article  Google Scholar 

  16. Khargharia, B., Hariri, S., Yousif, M.S.: An Adaptive Interleaving Technique for Memory Performance-per-Watt Management. IEEE Transactions on Parallel and Distributed Systems 20(7), 1011–1022 (2009)

    Article  Google Scholar 

  17. Sohi, G.S.: High-bandwidth interleaved memories for vector processors-a simulation study. IEEE Transactions on Computers 42(1), 34–44 (1993)

    Article  Google Scholar 

  18. Song, C., Postula, A.: Synthesis of custom interleaved memory systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8(1), 74–83 (2000)

    Article  Google Scholar 

  19. VanCourt, T., Herbordt, M.C.: Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations. In: IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 305–306 (2006)

    Google Scholar 

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© 2011 Springer-Verlag Berlin Heidelberg

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Morita, H., Watanabe, M. (2011). MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_25

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  • DOI: https://doi.org/10.1007/978-3-642-19475-7_25

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-19474-0

  • Online ISBN: 978-3-642-19475-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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