A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology

Abstract

This paper describes the architecture of a reconfigurable Complex Programmable Logic Device (CPLD) designed for structured ASIC technology. The proposed architecture adds the feature of reconfiguration to structured ASIC with both static and dynamic reconfiguration options. Static reconfiguration is realized using the possibility to reprogram the SRAM based look-up tables at power-up while dynamic reconfiguration uses embedded memory to implement a multi-context device. Dynamic reconfiguration is realized by storing sixteen CPLD configurations in on-chip memory. This inactive on-chip memory is distributed around the chip allowing single cycle configuration change and it can be accessed either from off-chip or from internal logic. Implementation results on structured ASIC validated the solution from both area and timing perspective.