Abstract
Many modern microprocessor architectures utilize simultaneous multithreading (SMT) for increased performance. This trend is exemplified in IBM’s Power series of high-end microprocessors which steadily increased the number of threads in a system in its POWER5, POWER6 and POWER7 designs. In this paper we discuss the steady increase in functional verification complexity introduced by each of these designs and the corresponding improvements to SMT verification methods that were necessary in order to cope with the growing verification challenge. We review three different verification technologies which were specifically developed to target SMT aspects of processor designs, and compare their relative advantages and drawbacks. Our focus is on the novel Thread Irritation technique – we demonstrate its effectiveness in finding high quality SMT bugs early in the verification cycle, and show how it was adopted to the post-silicon platform.
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Ludden, J.M., Rimon, M., Hickerson, B.G., Adir, A. (2011). Advances in Simultaneous Multithreading Testcase Generation Methods. In: Barner, S., Harris, I., Kroening, D., Raz, O. (eds) Hardware and Software: Verification and Testing. HVC 2010. Lecture Notes in Computer Science, vol 6504. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19583-9_15
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DOI: https://doi.org/10.1007/978-3-642-19583-9_15
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