Abstract
If there were only one type of parallel hardware then perhaps the problem of designing programming languages for this domain would be tractable. Unfortunately, there are many: multicores, SMPs, MPSoCs, FPGAs, GPGPUs and dataflow machines to name just a few. And even the single architecture of ‘multicore’ represents a host of alternatives specifically with respect to memory management and scale. The scale issue being a particular source of concern – dual and four cores chips are currently problematic, but we know 1024 cores are not too far away. Even a focus of 1024 cores is sometimes criticized as being redundant and a wasted effort as 10,000 cores per chip is just around the corner.
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Burns, A., Davis, R.I., Wang, P., Zhang, F.: Partitioned EDF scheduling for multiprocessors using a C=D scheme. In: Proceedings of 18th International Conference on Real-Time and Network Systems (RTNS), pp. 169–178 (2010)
Burns, A., Wellings, A.J.: Dispatching domains for multiprocessor platforms and their representation in ada. In: Real, J., Vardanega, T. (eds.) Ada-Europe 2010. LNCS, vol. 6106, pp. 41–53. Springer, Heidelberg (2010)
Davis, R.I., Burns, A.: A survey of hard real-time scheduling algorithms for multiprocessor systems. Accepted for publication in ACM Computing Surveys (2011)
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Burns, A. (2011). Programming Languages for Real-Time Applications Executing on Parallel Hardware. In: Romanovsky, A., Vardanega, T. (eds) Reliable Software Technologies - Ada-Europe 2011. Ada-Europe 2011. Lecture Notes in Computer Science, vol 6652. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21338-0_15
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DOI: https://doi.org/10.1007/978-3-642-21338-0_15
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