Abstract
Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers are indispensable part of DSP processing, FFT, convolution and many more areas where computation is required. In this paper an improved optimized design of 32-bit unsigned array multiplier with low power and reduced area is proposed. The power dissipation of optimized multiplier design is reduced by 3.82 percent and more than 30 percent as compared to multipliers using ripple carry and carry select adders. The area reduction is highly achieved by reducing the gate count.
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Devi, P., Singh, G.p., singh, B. (2011). Low Power Optimized Array Multiplier with Reduced Area. In: Mantri, A., Nandi, S., Kumar, G., Kumar, S. (eds) High Performance Architecture and Grid Computing. HPAGC 2011. Communications in Computer and Information Science, vol 169. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22577-2_30
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DOI: https://doi.org/10.1007/978-3-642-22577-2_30
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