Abstract
In ATPG, faults in the VLSI circuits are detected with D-algorithm, SPODEM and FAN algorithms. This paper gives the emphasis on presenting first two algorithms in MATLAB. Implementation of these algorithms for complex VLSI circuits is very tedious job. So an environment in Simulink is presented here, which is further verified on some benchmark circuits. Simulink provides an environment for intellectual properties (IP) building block based circuit engineering design as well as project simulation environment. In PODEM the requirement is the exact values of Controllability and Observability. For effective and fast calculation of COM, Simulink based designed models are used.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Sziray, J.: Computational Complexity in Logic testing. Intelligent Engineering system (INES). In: 14th international Conference, Las Palmas of Grain Canaria, Spain, May 4-7, pp. 97–102 (2010)
Inoue, T., Izumi, N., Yoshikawa, Y., Ichhihra, H.: A Fast Threshold Generation Algorithm Based on 5-Valued Logic. In: 5th IEEE International Symposium on Electronic Design, Test & Applications, pp. 345–349 (2010)
Jayanthy, S., Bhuvaneswari, M.C.: Simulation Based ATPG for Crosstalk Delay Faults in VLSI Circuits using Genetic Algorithm. ICGST-AIM Journal 9(2), 11–17 (2009)
Efthymioy, A.: Redundancy and Test-Pattern Generation for Asynchronous Quasi-delay-Insensitive Combinational Circuits. Design & Diagnostics of Electronic Circuits and Systems (2007)
Perelroyzen, E.: Digital Integrated Circuits Design for test Using Simulink and State flow, pp. 143–193. CRC Press Taylor&Francis Group (2007)
Wang, L.-T., Wu, C.-W.: VLSI test Principles and Architectures design for testability., pp. 11–21, 37-48, 161-244. Margen Kaufmann Publishers, San Francisco (2006)
Grout, I.A.: Integrated circuit test engineering, 3rd edn., pp. 41–85. Springer, London (2006)
Vaseekar Kumar, M.M., Padmanaban, S., Tragoudas, S.: Low Power ATPG for Path Delay Faults. In: Proceeding of the 14th ACM Great Lakes Symposium on VLSI, April26-28, pp. 398–392 (2004)
Bushnell, M.L., Agrawal, V.D.: Essential of Electronic Testing for Digital Memory & Mixed-Signal VLSI Circuits, pp. 81–206. Kluwer Acadmic Publishers, Dordrecht (2004)
Using Simulink: Dynamic System Simulation for MATLAB. The Mathworks, Inc., Natick, MA (2004)
Marchand, P., Thomas Holland, O.: Graphics and GUIS with Matlab, 3rd edn., ch. 10. Chapman and Hall/CRC (2003)
Jha, N.K., Gupta, S.: Testing of Digital system, 1st edn., pp. 266–306. Cambridge university Press, Cambridge (2003)
Miczo, A.: Digital Logic testing and Simulation, 2nd edn., pp. 119–128, 165-201. A John Willey & Sons, West Sussex (2003)
Kamiura, N., Isokawa, T., Mastsui, N.: PODEM based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits. In: Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (2002)
Chapman, S.J.: MATLAB programming for Engineers, a division of Thomson learning USA, 2nd edn (2002)
Kamiura, N., Hata, Y., Matsui, N.: Controllability /Observability Measures for multiple-valued test generation based on D-algorithm. In: 30th IEEE international Proceeding, ISMVL (2000)
Kirovski, D., Potkonjank, M., Guerra, L.M.: Improving the Observability and Controllability of Data paths for Emulation-Based Debugging. IEEE Transaction on Computer-Aided Design Of Integrated Circuits and Systems 18(11), 1529–1536 (1999)
Hamzaoglu, I., Patel, J.H.: New Techniques for Deterministic Test Pattern Generation. In: 16th IEE Proceedings VLSI test Symposium (1998)
Shmerko, V.P., Yanushkevich, S., Levashenko, V.: Test Pattren Generation for Combinational Multi-Valued Networks based on Generalized D-algorithm. In: 27th international symposium preceding, pp. 139–144 (1997)
Jone, W.-B., Shah, N., Gleason, A., Das, S.R.: PGEN: A Novel Approach to Sequential Circuit Test Generation. VLSI design. OPA (oversea publishers association) 4(3), 149–165 (1996)
Hong, S.J.: A 15-valued Fast Test Generation for Combinational Circuits. In: IEEE Test Symposium, pp. 113–118 (1993)
Jamoussi, M., Kamonska, B.: Controllability and Observability Measures For functional-Level Testability Evalution. In: IEEE VLSI Test Symposium, pp. 211–216 (1992)
Butler, K.M., Kapur, R., Ray Mercer, M., Ross, D.E.: The Role Of Controllability and Observability in Design for Test. In: IEEE VLSI Test Symposium, pp. 154–157 (1992)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Singh, G.P., Singh, B. (2011). Simulink Library Development and Implementation for VLSI Testing in Matlab. In: Mantri, A., Nandi, S., Kumar, G., Kumar, S. (eds) High Performance Architecture and Grid Computing. HPAGC 2011. Communications in Computer and Information Science, vol 169. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22577-2_31
Download citation
DOI: https://doi.org/10.1007/978-3-642-22577-2_31
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-22576-5
Online ISBN: 978-3-642-22577-2
eBook Packages: Computer ScienceComputer Science (R0)