Abstract
This paper proposes a method to implement fault-tolerant self-reconfigurable 2D systolic arrays to calculate matrix multiplications on FPGAs. The array uses a 1.5-track switching network for reconfiguration. The array implemented is compared to the corresponding non-redundant case by simulations of concrete examples, in terms of hardware size, total array reliability where not only faults of processing elements but also faults in the 1.5-track switching network are considered, computation time and electricity consumption. The simulation results show that the fault-tolerant array is better than the corresponding non-redundant one, in terms of the total array reliability, even if faults in the 1.5-track switching network are not negligible. In Appendix, we discuss the relation between the fault rates of the proposed fault-tolerant array and the corresponding non-redundant one and show that the former can be significantly decreased for the array of large size.
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Lim, H., Piuri, V., Swartzlander, E.E.: A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms. IEEE Trans. on Comput. 49(12), 1297–1309 (2000)
Kung, S.Y., Jean, S.N., Chang, C.W.: Fault-tolerant array processors using single-track switches. IEEE Trans. Comput. 38(4), 501–514 (1989)
Shigei, N., Miyajima, H.: On the search for effective spare arrangement for reconfigurable processor arrays using genetic algorithm. IEICE Trans. Fundamentals E81-A(9), 1898–1901 (1998)
Kim, G., Yoon, H.: On submesh allocation for mesh multicomputers: A best-fit allocation and a virtual submesh allocation for faulty meshes. IEEE Trans. Parallel and Distributed Systems 9(2), 175–185 (1998)
Yamada, T., Ueno, S.: Fault-tolerant meshes with efficient layouts. IEICE Trans. Inf. & Syst. E81-D(1), 56–65 (1998)
LaForge, L.E.: What designers of microelectronic systems should know about arrays spared by rows and columns. IEEE Trans. Reliability 49(3), 251–272 (2000)
Zhang, L.: Fault-tolerant meshes with small degree. IEEE Trans. Comput. 51(5), 553–560 (2002)
Low, C.P.: An efficient reconfiguration algorithm for degradable VLSI/WSI arrays. IEEE Trans. Comput. 49(6), 553–559 (2000)
Horita, T., Takanami, I.: Fault tolerant processor arrays based on the 1\(\frac{1}{2}\)-track switches with flexible spare distributions. IEEE Trans. Comput. 49(6), 542–552 (2000)
Horita, T., Takanami, I.: A built-in self-reconstruction approach for partitioned mesh-arrays using neural algorithm. IEICE Trans. Inf. & Syst. E79-D(8), 1160–1167 (1996)
Horita, T., Takanami, I.: A system for efficiently self-reconstructing 1\(\frac{1}{2}\)-track switch torus arrays. IEICE Trans. Inf. & Syst. E84-D(12), 1801–1809 (2001)
Horita, T., Takanami, I.: A system for efficiently self-reconstructing array system using E-1\(\frac{1}{2}\)-track switches. IEICE Trans. Inf. & Syst. E86-D(12), 2743–2752 (2003)
Horita, T., Takanami, I.: The total system reliabilities for fault-tolerant self-reconfigurable array systems. In: Advances in Computer Science and Engineering, vol. 2(2), pp. 165–187. Pushpa Publishing House (2008)
Horita, T., Yamashita, T., Takanami, I.: A reliability analysis for various fault-tolerant 2D processor arrays using 1.5-track switches. In: Advances in Computer Science and Engineering, vol. 2(3), pp. 243–266. Pushpa Publishing House (2008)
Horita, T., Katou, Y., Takanami, I.: An analysis for fault-tolerant 3D processor arrays using 1.5-track switches. IEICE Trans. Fundamentals E91-A(2), 623–632 (2008)
Bednara, M., Daldrup, M., Teich, J., von zur Gathen, J., Shokrollahi, J.: Tradeoff analysis of FPGA based elliptic curve cryptography. In: Proc. IEEE Int’l Symp. on ISCAS 2002, vol. 5, pp. 797–800 (2002)
Ors, S.B., Batina, L., Preneel, B., Vandewalle, J.: Hardware implementation of a montgomery modular multiplier in a systolic array. In: Proc. IEEE Int’l Symp. on IPDPS 2003, pp. 184–192 (2003)
Wang, Y.B., Dong, X.J., Tian, Z.G.: FPGA based design of elliptic curve cryptography coprocessor. In: Proc. Int’l Conf. on ICNC 2007, vol. 5, pp. 185–189 (2007)
Kim, Y., Jeong, H.: A systolic FPGA architecture of two-level dynamic programming for connected speech recognition. IEICE Trans. Inf. & Syst. E90-D(2), 562–568 (2007)
Fukushi, M., Horiguchi, S.: Self-reconfigurable mesh array system on FPGA. In: Proc. IEEE Intl Symp. on DFT, pp. 240–248 (2000)
Horita, T., Takanami, I.: An implementation of a fault-tolerant 2D systolic array on FPGAs and its evaluation. In: Proc. CSREA Int’l Conf. on Technologies and Applications PDPTA 2009, pp. 136–142 (2009)
Altera reliability report homepage (2009), http://www.altera.com/literature/rr/rr.pdf
Horita, T., Takanami, I.: An efficiently reconfigurable architecture for mesh-arrays with PE and link faults. IEICE Trans. Inf. & Syst. E80-D(9), 879–885 (1997)
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Horita, T., Takanami, I. (2011). An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications. In: Gavrilova, M.L., Tan, C.J.K. (eds) Transactions on Computational Science XIII. Lecture Notes in Computer Science, vol 6750. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22619-9_6
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DOI: https://doi.org/10.1007/978-3-642-22619-9_6
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