Skip to main content
SpringerLink
Log in

Research on Power Optimization Techniques for Multi Core Architectures

  • Conference paper
Advances in Computing and Communications (ACC 2011)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 190))

Included in the following conference series:

Abstract

Continuous effort to achieve higher performance without driving up the power consumption and thermal effects has led the researchers to look for alternative architectures for microprocessors. Like the parallel processing which is extensively used in today’s all microprocessors, multi-core architecture which combines several independent microprocessor cores in a single die has currently become very popular in most high performance integrated circuits. Although multi-core processor offers excellent instruction execution speed with reduced power consumption, optimizing performance of individual processors and then incorporating them by interconnection on a single chip is a non-trivial task. This paper investigates the leading challenges associated with current high performance multi-core processor in terms of different types of power optimization techniques.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Wee, A.S.M., Tan, C.E., Lau, S.P.: Power optimization in multi-processor systems. In: International Symposium in Information Technology, ITSim, vol. 2, pp. 826–830 (2010)

    Google Scholar 

  2. Ahmad, I., Ranka, S., Khan, S.U.: Using Game Theory for Scheduling Tasks on Multi-Core Processors for Simultaneous Optimization of Performance and Energy. In: IEEE International Symposium Parallel and Distributed Processing, pp. 1–6 (2008)

    Google Scholar 

  3. Guo, D., Kuang, J., Bhuyan, L.: Power Optimization for Multimedia Transcoding on Multicore Servers. In: ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), pp. 1–2 (2010)

    Google Scholar 

  4. King, C.-T., Lin, K.-H., Tseng, S.-Y., Wang, W.-S., Chang, S.-H.: Performance and Power Consumption Analysis of DVFS Enabled H264 Decoderon Heterogeneous Multi-Core Platform. In: International Conference on Computer and Information Technology (CIT), pp. 1758–1763 (2010)

    Google Scholar 

  5. Garrett, D.: A Multicore-Enabled Framework for the Construction of Metaheuristics for Single and Multiobjective Optimization, pp. 351–360. Springer, Heidelberg (2010)

    Google Scholar 

  6. Lee, D.-W., Jung, E., Lee, J.-G.: Asymptotic Performance Analysis and Optimization of Resource-Constrained Multi-Core Architectures. In: International Conference on Microelectronics, pp. 462–465 (2008)

    Google Scholar 

  7. Deshpande, J.L., Srinivasan, A., Ma, J.X.: Energy and Performance Impact of Aggressive Volunteer Computing with Multi-core Computers. In: IEEE International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems, pp. 1–10 (2009)

    Google Scholar 

  8. Hong, C., Choi, H.J., Kim, J.-M., Park, Y.J.: Energy-aware Filter Cache Architecture for Multicore Processors. In: Fifth IEEE International Electronic Design, Test and Application, pp. 58–62 (2010)

    Google Scholar 

  9. Bergamaschi, R., Bose, P., Buyuktosunoglu, A., Dhanwada, N., Darringer, J., Dittmann, G., Han, G., IJanssen, G., Patel, H., Nair, Z.H.: Exploring Power Management in Multi-Core Systems. In: Asia and South Pacific Design Automation Conference, pp. 708–713 (2008)

    Google Scholar 

  10. Mishra, A.K., Das, C.R., Kandemir, M., Srikantaiah, S.: CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors. In: International Conference for High Performance Computing, Networking, Storage and Analysis (SC), pp. 1–12 (2010)

    Google Scholar 

  11. Xiang, L., Huang, J., Chen, T.: Coordinating System Software for Power Savings. International Journal of Advanced Science and Technology 2, 222–225 (2008), International Conference on Future Generation Communication and Networking

    Google Scholar 

  12. Vittoz, E.A., IEEE, Leblebici, Y., IEEE, Deniz, Z.T., IEEE: On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation. IEEE Journal of Solid-State Circuits 42(7), 1593–1606 (2007)

    Article  Google Scholar 

  13. Monchiero, M., Canal, R., González, A.: Power/Performance/Thermal Design-Space Exploration for Multicore Architectures. IEEE Transactions on Parallel and Distributed Systems 19(5) (2008)

    Google Scholar 

  14. Bautista, D., Duato, J., Sahuquillo, J., Hassan, H., Petit, S.: A Simple Power-Aware Scheduling for Multicore Systems when Running Real-Time Applications. In: IEEE International Symposium Parallel and Distributed Processing, pp. 1–7 (2008)

    Google Scholar 

  15. Chen, J., John, L.K.: Energy-Aware Application Scheduling on a Heterogeneous Multi-core System. In: IEEE International Symposium on Workload Characterization, pp. 5–13 (2008)

    Google Scholar 

  16. Cho, S., Melhem, R.G.: On the Interplay of Parallelization, Program Performance, and Energy Consumption. IEEE Transactions on Parallel and Distributed Systems 21(3), 342–353 (2010)

    Article  Google Scholar 

  17. Majzoub, S., Saleh, R., Wilton, S.J.E., Ward, R.: Removal-Cost Method: An Efficient Voltage Selection Algorithm for Multi-Core Platforms under PVT. In: IEEE Conferences, pp. 357–360 (2009)

    Google Scholar 

  18. Majzoub, S.S., Saleh, R.A., Wilton, S.J.E., Ward, R.K.: Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(5), 816–829 (2010)

    Article  Google Scholar 

  19. Jung, H., Pedram, M.: Supervised Learning Based Power Management for Multicore Processors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(9), 1395–1408 (2010)

    Article  Google Scholar 

  20. Jiao, J., Wang, H., Liu, T., Han, X., Fu, Y.: Multi-core System based on 3D Torus Network on Chip. In: 8th IEEE International NEWCAS Conference (NEWCAS), pp. 313–316 (2010)

    Google Scholar 

  21. Blake, G., Dreslinski, R.G., Mudge, T.: A Survey of Multicore Processors. IEEE Signal Processing Magazine 26(6), 26–37 (2009)

    Article  Google Scholar 

  22. Zheng, H., IEEE, Zhu, Z., IEEE: Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multi core Processors. IEEE Transactions on Computers 59(8), 1033–1046 (2010), IEEE Journals

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, Manonmanium Sundaranar University, Tirunelveli, India

    A. S. Radhamani

  2. Department of Computer Science and Engineering, Sun College of Engineering and Technology, Nagercoil, India

    E. Baburaj

Authors
  1. A. S. Radhamani
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. E. Baburaj
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Machine Intelligence Research Labs (MIR Labs), Auburn, 98071-2259, Washington, USA

    Ajith Abraham

  2. Department of Communications, Polytechnic University of Valencia, Camino de Vera, 46022, Valencia, Spain

    Jaime Lloret Mauri

  3. Avaya Labs Research, Basking Ridge, NJ, USA

    John F. Buford

  4. University of Massachusetts, 100 Morrissey Blvd., 02125-3393, Boston, MA, USA

    Junichi Suzuki

  5. Rajagiri School of Engineering and Technology, Rajagiri Valley, Kakkanad, 682 039, Kochi, India

    Sabu M. Thampi

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Radhamani, A.S., Baburaj, E. (2011). Research on Power Optimization Techniques for Multi Core Architectures. In: Abraham, A., Lloret Mauri, J., Buford, J.F., Suzuki, J., Thampi, S.M. (eds) Advances in Computing and Communications. ACC 2011. Communications in Computer and Information Science, vol 190. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22709-7_18

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-22709-7_18

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-22708-0

  • Online ISBN: 978-3-642-22709-7

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation