Exploiting ILP in a SIMD Type Vector Processor

Abstract

In this paper we exploit instruction level parallelism by compiler optimization techniques like loop unrolling and loop peeling for an SIMD type vector processor. SIMD type vector processor is a high performance computational model which exploits the computational capabilities of both SIMD and vector architecture. SIMD type vector processor works on short vector instructions of vector length four and has four processing units which enables execution of four vector operands simultaneously. To implement the proposed work we need a common estimation platform. We use MachSUIF intermediate representation for proposed approach. MachSUIF is provided with many inbuilt passes which gives us different levels of intermediate representations. We have created a control data flow graph (CDFG) to do vectorization according to SIMD type vector architecture. We have made a custom pass in MachSUIF in which we do unrolling and peeling according to the architecture i.e. we will be unrolling the loop to size four. We have shown that in ideal conditions we will get a speed up factor of 4 in a SIMD type vector processor.