Abstract
As the computation demands increases to meet the design requirements for computation-intensive applications, the pressure to develop high performance parallel processors on a chip is increasing. However, software supports that enable harnessing parallel computing power of this type of architecture have not followed suit and it has become an important stumbling block for future many core application developments. In this paper, we introduce a cycle-accurate simulator for parallel programming on many-core platform, enabling fast design space exploration.
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Lee, S.E. (2011). Cycle Accurate Power and Performance Simulator for Design Space Exploration on a Many-Core Platform. In: Lin, S., Huang, X. (eds) Advances in Computer Science, Environment, Ecoinformatics, and Education. CSEE 2011. Communications in Computer and Information Science, vol 215. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-23324-1_28
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DOI: https://doi.org/10.1007/978-3-642-23324-1_28
Publisher Name: Springer, Berlin, Heidelberg
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