Abstract
In this paper, a novel and systematic LDPC codeword construction and verification methodology is proposed. The methodology is composed by the simulated annealing based LDPC codeword constructor, the GPU based high-speed codeword selector and the ant colony optimization based pipeline scheduler. Compared to the traditional ways, this methodology enables us to construct both decoding-performance-aware and hardware-efficiency-aware LDPC codewords in a short time. Simulation results show that the generated codewords have much less cycles (length 6 cycles eliminated) and memory conflicts (75% reduction on idle clocks), while having no BER performance loss compared to WiMAX codewords. Additionally, the simulation speeds up by 490 times under float precision against CPU and a net throughput 24.5Mbps is achieved.
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Cui, J., Wang, Y., Yu, H. (2011). Systematic Construction and Verification Methodology for LDPC Codes. In: Cheng, Y., Eun, D.Y., Qin, Z., Song, M., Xing, K. (eds) Wireless Algorithms, Systems, and Applications. WASA 2011. Lecture Notes in Computer Science, vol 6843. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-23490-3_34
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DOI: https://doi.org/10.1007/978-3-642-23490-3_34
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