Skip to main content

An Efficient Hardware Countermeasure against Differential Power Analysis Attack

  • Conference paper
Convergence and Hybrid Information Technology (ICHIT 2011)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 206))

Included in the following conference series:

  • 1759 Accesses

Abstract

Extensive research on modern cryptography ensures significant mathematical immunity to conventional cryptographic attacks. However, power consumption in cryptographic hardware leak secret information. Differential power analysis attack (DPA) is such a powerful tool to extract the secret key from cryptographic devices. To defend against these DPA attacks, hiding and masking methods are widely used. But these methods increase high area overhead and performance degradation in hardware implementation. In this aspect, this paper proposes a hardware countermeasure circuit, which, is integrated hardware module with the intermediate stages in S-Box. The countermeasure circuit utilizes the dynamic power dissipation characteristics of CMOS and provides countermeasure against DPA attacks.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Quisquater, J.J., Rizk, M.: Side Channel attacks. Information-technology promotion agency, Japan technical report (October 2002) http://www.ipa.go.jp/security/enc/CRYPTREC/fy15/doc/1047_Side_Channel_report.pdf

  2. Kocher, P.C., Jaffe, J., Jun, B.: Differential power analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, p. 388. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  3. Brier, E., Clavier, C., Olivier, F.: Correlation Power Analysis with a Leakage Model. In: vol. 1. Springer, Heidelberg (1973); vol. 6697 (2011), 0302-9743 (Print) 1611-3349 (Online)

    Google Scholar 

  4. Clavier, C., Coron, J.-S., Dabbous, N.: Differential power analysis in the presence of hardware countermeasures. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 252–263. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  5. Coron, J.-S., Goubin, L.: On Boolean and arithmetic masking against differential power analysis. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 231–237. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  6. Coron, J.-S., Kocher, P.C., Naccache, D.: Statistics and secret leakage. In: Frankel, Y. (ed.) FC 2000. LNCS, vol. 1962, pp. 157–173. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  7. Mayer-Sommer, R.: Smartly analyzing the simplicity and the power of simple power analysis on smartcards. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 78–92. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  8. Messerges, T.S.: Using second-order power analysis to attack DPA resistant software. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 238–252. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  9. Messerges, T., Dabbish, E., Sloan, R.: Investigation of power analysis attacks on smartcards. In: Usenix Workshop on Smartcard Technology (1999), http://www.usenix.org

  10. Liu, P.-C., Chang, H.-C., Lee, C.-Y.: Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators. IEEE Transactions on Circuits and Systems 57(7), 546–550

    Google Scholar 

  11. Danis, A.U., Berna, O.: Differential Power Analysis Attack Considering Decoupling Capacitance Effect. In: European Conference on Circuit Theory and Design, ECCTD 2009, pp. 358–362 (October 2009)

    Google Scholar 

  12. Semenov, O., Vassighi, A., Sachdev, M., Ali, K., Hawkins, C.F.: Burn-in Temperature Projections for Deep Sub-micron Technologies. In: Proceedings of International Test Conference, ITC 2003, pp. 95–104 (2003)

    Google Scholar 

  13. Pramstaller, N., Oswald, E., Mangard, S., Gürkaynak, F.K., Häne, S.: A masked AES ASIC implementation. In: Proc. Austrochip, pp. 77–82 (2004)

    Google Scholar 

  14. Akkar, M.-L., Giraud, C.: An implementation of DES and AES, secure against some attacks. In: Proc. CHES 2001, pp. 309–318 (2001)

    Google Scholar 

  15. Trichina, E., Seta, D.D., Germani, L.: Simplified adaptive multiplicative masking for AES. In: Proc. CHES 2002, pp. 71–85 (2002)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Choudhury, A.J., Park, B.S., Bruce, N., Lee, Y.S., Lim, H., Lee, H.J. (2011). An Efficient Hardware Countermeasure against Differential Power Analysis Attack. In: Lee, G., Howard, D., Ślęzak, D. (eds) Convergence and Hybrid Information Technology. ICHIT 2011. Communications in Computer and Information Science, vol 206. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24106-2_20

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-24106-2_20

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-24105-5

  • Online ISBN: 978-3-642-24106-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics