Abstract
Scaling DRAM will be increasingly difficult due to power and cost constraint. Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM incurs relatively long latency , high write energy, and finite endurance. To make PCM an alternative for scalable main memory, write traffic to PCM should be reduced, where memory replacement policy could play a vital role.
In this paper, we propose a Read-Write Aware policy (RWA) to reduce write traffic without performance degradation. RWA explores the asymmetry of read and write costs of PCM, and prevents dirty data lines from frequent evictions. Simulations results on an 8-core CMP show that for memory organization with and without DRAM buffer, RWA can achieve 33.1% and 14.2% reduction in write traffic to PCM respectively. In addition, an Improved RWA (I-RWA) is proposed that takes into consideration the write access pattern and can further improve memory efficiency. For organization with DRAM buffer, I-RWA provides a significant 42.8% reduction in write traffic. Furthermore, both RWA and I-RWA incurs no hardware overhead and can be easily integrated into existing hardware.
This work is supported by Nature Science Foundation of China (No. 60833004, 60970002), and the National 863 High Technology Research Program of China (No.2008AA01A201).
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References
Lefurgy, C., et al.: Energy management for commercial servers. IEEE Computer 36(12), 39–48 (2003)
Int’l Technology Roadmap for Semiconductors:Process Integration, Devices, and Structures, Semiconductor Industry Assoc. (2007), http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_PIDS.pdf
Kgil, T., Roberts, D., Mudge, T.: Improving NAND Flash Based Disk Caches. In: The 35th International Symposium on Computer Architecture, pp. 327–338 (2008)
Wu, M., Zwaenepoel, W.: eNVy: A Nonvolatile, Main Memory Storage System. In: ASPLOS-VI, pp. 86–97 (1994)
Raoux, S., et al.: Phase-change random access memory: A scalable technology. IBM Journal of R. and D. 52(4/5), 465–479 (2008)
Kanellos, M.: IBM Changes Directions in Magnetic Memory (August 2007), http://news.cnet.com/IBM-changes-directions-in-magneticmemory/2100-10043-6203198.html
Intel. Intel, STMicroelectronics Deliver Industry’s First Phase Change Memory Prototypes. Intel News Release (February 6, 2008)
Wu, X., et al.: Hybrid cache architecture with disparate memory technologies. In: ISCA 2009, pp. 34–45 (2009)
Kang, D.H., et al.: Two-bit Cell Operation in Diode-Switch Phase Change Memory Cells with 90nm Technology. In: IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 98–99 (2008)
Qureshi, M., et al.: Scalable high performance main memory system using phase-change memory technology. In: ISCA-36 (2009)
The Basics of Phase Change Memory Technology, http://www.numonyx.com/Documents/WhitePapers/PCM_Basics_WP.pdf
Kalla, R., Sinharoy, B., Starke, W.J., Floyd, M.: Power7: IBM’s Next-Generation Server Processor. IEEE Micro. 30(2), 7–15 (2010)
Virtutech AB. Simics Full System Simulator, http://www.simics.com/
Wisconsin Multifacet GEMS Simulator, http://www.cs.wisc.edu/gems/
Park, S.-Y., Jung, D., Kang, J.-U., Kim, J.-S., Lee, J.: CFLRU: a replacement algorithm for flash memory. In: Proc. of International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 234–241 (2006)
Jung, H., et al.: LRU-WSR: integration of LRU and writes sequence reordering for flash memory. Trans. on Cons. Electr. 54(3), 1215–1223 (2008)
Seo, D., Shin, D.: Recently-evicted-first buffer replacement policy for flash storage devices. Trans. on Cons. Electr. 54(3), 1228–1235 (2008)
Qureshi, M., Jaleel, A., Patt, Y., Steely, S., Emer, J.: Adaptive Insertion Policies for High Performance Caching. In: ISCA-34, pp. 167–178 (2007)
Jaleel, A.K.B., Theobald Jr., S.C.S., Emer, J.: High performance cache replacement using re-reference interval prediction (RRIP). In: ISCA-37, pp. 60–71 (2010)
Dhiman, G., et al.: PDRAM: A hybrid PRAM and DRAM main memory system. In: DAC 2009, pp. 664–669 (2009)
Zhou, P., et al.: A durable and energy efficient main memory using phase change memory technology. In: ISCA-36 (2009)
Cho, S., et al.: Flip-N-Write: A simple deterministic technique to improve pram write performance, energy and endurance. In: MICRO-42 (2009)
Wu, X., et al.: Power and Performance of Read-Write Aware Hybrid Caches with Non-volatile Memories. In: DATE 2009 (2009)
Qureshi, M.K., Franceschini, M., Lastras, L.: Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing. In: HPCA-16 (2010)
Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 Programs: Characterization and Methodological Considerations. SIGARCH Comput. Archit. News 23(2), 24–36 (1995)
Bienia, C., Kumar, S., Clara, S., Singh, J.P., Li, K.: The PARSEC Benchmark Suite: Characterization and Architectural Implications. In: PACT-17, pp. 272–281 (2008)
UltraSPARC T2 supplement to the UltraSPARC architecture 2007. Draft D1.4.3 (2007)
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Zhang, X., Hu, Q., Wang, D., Li, C., Wang, H. (2011). A Read-Write Aware Replacement Policy for Phase Change Memory. In: Temam, O., Yew, PC., Zang, B. (eds) Advanced Parallel Processing Technologies. APPT 2011. Lecture Notes in Computer Science, vol 6965. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24151-2_3
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DOI: https://doi.org/10.1007/978-3-642-24151-2_3
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