Abstract
This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction memory (IM) and a data memory (DM), while the multi-core architecture consists of PCs, individual IMs for each core, a shared DM and an interconnection crossbar between the cores and the DM. These architectures are compared with respect to power vs performance trade-offs for a multi-lead electrocardiogram signal conditioning application exploiting near threshold computing. The results show that the multi-core solution consumes 66% less power for high computation requirements (50.1 MOps/s), whereas 10.4% more power for low computation needs (681 kOps/s).
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Mamaghanian, H., et al.: Compressed Sensing for Real-Time Energy-Efficient ECG Compression on Wireless Body Sensor Nodes. IEEE Transactions on Biomedical Engineering 12, 120–129 (2011)
Hanson, M.A., et al.: Body Area Sensor Networks: Challenges and Opportunities. IEEE Computer 42, 58–65 (2009)
Rincon, F., et al.: Multi-Lead Wavelet-Based ECG Delineation on a Wearable Embedded Sensor Platform. Computers in Cardiology, 289–292 (2010)
Hanson, S., et al.: Exploring variability and performance in a sub-200 mV processor. IEEE J. Solid-State Circuits 43, 881–891 (2008)
Zhai, B., et al.: A 2.60 pJ/Inst subthreshold sensor processor for optimal energy efficiency. In: Symposium on VLSI Circuits. Digest of Technical Papers, Honolulu (2006)
Wang, A., Chandrakasan, A.: A 180 mV FFT processor using sub- threshold circuit techniques. In: IEEE Int. Solid-State Circuits Conference. Dig. Tech. Papers (2004)
Dreslinski, R.G., et al.: Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated Circuits. Proceedings of the IEEE 98, 253–266 (2010)
Chen, G., et al.: Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells. In: Solid-State Circuits Conference. Digest of Technical Papers, San Francisco (2010)
Hanson, S., et al.: A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode. IEEE J. Solid-State Circuits 44, 1145–1155 (2009)
Dreslinkski, R.G., et al.: An Energy Efficient Parallel Architecture Using Near Threshold Operation. In: 16th International Conference on Parallel Architecture and Compilation Techniques, Brasov, pp. 175–188 (2007)
Yu, P., et al.: An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. IEEE J. Solid-State Circuits 45, 668–680 (2010)
Krimer, E., et al.: Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications. Computer Architecture Letters 9, 21–24 (2010)
Sun, Y., et al.: ECG signal conditioning by morphological filtering. Computers in Biology and Medicine 32(6), 465–479 (2002)
Rahimi, A., et al.: A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1–6 (2011)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Dogan, A.Y., Atienza, D., Burg, A., Loi, I., Benini, L. (2011). Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing. In: Ayala, J.L., GarcÃa-Cámara, B., Prieto, M., Ruggiero, M., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2011. Lecture Notes in Computer Science, vol 6951. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24154-3_11
Download citation
DOI: https://doi.org/10.1007/978-3-642-24154-3_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-24153-6
Online ISBN: 978-3-642-24154-3
eBook Packages: Computer ScienceComputer Science (R0)