Abstract
3D integration has become one of the most promising techniques for the integration future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This paper proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ”traditional” thermal-aware floorplanners.
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References
Electrothermal monte carlo modelling of submicron hfets (2004), http://www.nanofolio.org/research/paper03.php
Intel tries to keep it cool (2004), http://www.pcworld.idg.com.au/article/108386/inteltrieskeepitscool
Adya, S., et al.: Fixed-outline floorplanning: enabling hierarchical design. IEEE Transactions on VLSI Systems 11(6), 1120–1135 (2003)
ARM: http://www.arm.com/products/processors/cortex-a/cortex-a9.php
Berntsson, J., Tang, M.: A slicing structure representation for the multi-layer floorplan layout problem. In: Raidl, G.R., Cagnoni, S., Branke, J., Corne, D.W., Drechsler, R., Jin, Y., Johnson, C.G., Machado, P., Marchiori, E., Rothlauf, F., Smith, G.D., Squillero, G. (eds.) EvoWorkshops 2004. LNCS, vol. 3005, pp. 188–197. Springer, Heidelberg (2004)
Borkar, S.: Design challenges of technology scaling. IEEE Micro 19(4) (1999)
Chen, G., et al.: Partition-driven standard cell thermal placement (2003)
Chu, C., et al.: A matrix synthesis approach to thermal placement. IEEE Transactions on CADICS 17(11), 1166–1174 (1998)
Coello, C., et al.: Evolutionary Algorithms for Solving Multi-Objective Problems. Kluwer, Dordrecht (2002)
Cong, J., et al.: A thermal-driven floorplanning algorithm for 3D ICs (2004)
Cuesta, D., Risco, J.L., Ayala, J.L., Atienza, D.: 3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems. In: IEEE Latin-American Test Workshop (2011)
Deb, K., et al.: A Fast and Elitist Multiobjective Genetic Algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation 6(2), 182–197 (2002)
Ekpanyapong, M., et al: Thermal-aware 3D microarchitectural floorplanning. Tech. rep., Georgia Institute of Technology Center (2004)
Han, Y., et al.: Simulated annealing based temperature aware floorplanning (2007)
Healy, M., et al.: Multiobjective microarchitectural floorplanning for 2D and 3D ICs. IEEE Transactions on CADICS 26(1), 38–52 (2007)
Hung, W.L., et al.: Thermal-aware floorplanning using genetic algorithms. In: ISQED, pp. 634–639 (March 2005)
IBM, C.D.C.: Complex soc design (2009)
Imperas: http://www.ovpworld.org
Iqbal, S., et al.: ParMiBench - an open-source benchmark for embedded multiprocessor systems. CAL 9(2), 45–48 (2010)
Li, X., et al.: A novel thermal optimization flow using incremental floorplanning for 3D ICs. In: ASPDAC, pp. 347–352. IEEE Press, Los Alamitos (2009)
Li, Y., et al.: Temperature aware floorplanning via geometry programming. In: IEEE International Conference on CSE Workshops, pp. 295–298 (July 2008)
Liu, Y., et al.: Accurate temperature-dependent integrated circuit leakage power estimation is easy. In: DATE, pp. 1526–1531 (2007)
OpenSPARC (2007), http://www.opensparc.net/pubs/preszo/07/n2isscc.pdf
Paci, G., et al.: Exploring temperature-aware design in low-power MPSoCs. International Journal of Embedded Systems 3(1), 43–51 (2007)
Sankaranarayanan, K., et al.: A case for thermal-aware floorplanning at the microarchitectural level. JILP 7(1), 8–16 (2005)
Singhal, L., et al.: Statistical power profile correlation for realistic thermal estimation. In: ASP-DAC, pp. 67–70. IEEE Computer Society Press, Los Alamitos (2008)
Tang, M., et al.: A memetic algorithm for VLSI floorplanning. IEEE Transactions on Systems, Man, and Cybernetics, Part B 37(1), 62–69 (2007)
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Arnaldo, I., Risco-Martín, J.L., Ayala, J.L., Hidalgo, J.I. (2011). Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures. In: Ayala, J.L., García-Cámara, B., Prieto, M., Ruggiero, M., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2011. Lecture Notes in Computer Science, vol 6951. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24154-3_2
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DOI: https://doi.org/10.1007/978-3-642-24154-3_2
Publisher Name: Springer, Berlin, Heidelberg
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