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Computer Architecture

ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised Selected Papers

  • Conference proceedings
  • © 2012

Overview

Editors:
  1. Ana Lucia Varbanescu

    1. Software Technologies Department, Delft University of Technology, Delft, The Netherlands

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  2. Anca Molnos

    1. Software Technologies Dept, Delft University of Technology, Delft, The Netherlands

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    You can also search for this editor in PubMed   Google Scholar

  3. Rob Nieuwpoort

    1. Department of Computer Science, Vrije Unversiteit Amsterdam, Amsterdam, The Netherlands

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 6161)

Part of the book sub series: Information Systems and Applications, incl. Internet/Web, and HCI (LNISA)

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Conference proceedings info: ISCA 2010.

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About this book

This book constitutes the thoroughly refereed post-conference proceedings of the workshops held at the 37th International Symposium on Computer Architecture, ISCA 2010, in Saint-Malo, France, in June 2010. The 28 revised full papers presented were carefully reviewed and selected from the lectures given at 5 of these workshops. The papers address topics ranging from novel memory architectures to emerging application design and performance analysis and encompassed the following workshops: A4MMC, applications for multi- and many-cores; AMAS-BT, 3rd workshop on architectural and micro-architectural support for binary translation; EAMA, the 3rd Workshop for emerging applications and many-core architectures; WEED, 2nd Workshop on energy efficient design, as well as WIOSCA, the annual workshop on the interaction between operating systems and computer architecture.

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Table of contents (28 papers)

  1. Front Matter

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  2. A4MMC: Applications for Multi- and Many-Cores

    1. Accelerating Agent-Based Ecosystem Models Using the Cell Broadband Engine

      • Michael Lange, Tony Field
      Pages 1-12

    2. Performance Impact of Task Mapping on the Cell BE Multicore Processor

      • Jörg Keller, Ana Lucia Varbanescu
      Pages 13-23

    3. Parallelization Strategy for CELL TV

      • Motohiro Takayama, Ryuji Sakai
      Pages 24-27

    4. Towards User Transparent Parallel Multimedia Computing on GPU-Clusters

      • Ben van Werkhoven, Jason Maassen, Frank J. Seinstra
      Pages 28-39

    5. Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture

      • Stephen M. Kofsky, Daniel R. Johnson, John A. Stratton, Wen-mei W. Hwu, Sanjay J. Patel, Steven S. Lumetta
      Pages 40-51

    6. On the Use of Small 2D Convolutions on GPUs

      • Shams A. H. Al Umairy, Alexander S. van Amesfoort, Irwan D. Setija, Martijn C. van Beurden, Henk J. Sips
      Pages 52-64

    7. Can Manycores Support the Memory Requirements of Scientific Applications?

      • Milan Pavlovic, Yoav Etsion, Alex Ramirez
      Pages 65-76

    8. Parallelizing an Index Generator for Desktop Search

      • David J. Meder, Walter F. Tichy
      Pages 77-85

  3. AMAS-BT: 3rd Workshop on Architectural and Micro-Architectural Support for Binary Translation

    1. Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks

      • Martha A. Kim, Stephen A. Edwards
      Pages 86-98

    2. Trace Execution Automata in Dynamic Binary Translation

      • João Porto, Guido Araujo, Edson Borin, Youfeng Wu
      Pages 99-116

    3. ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation

      • Maxwell Souza, Daniel Nicácio, Guido Araújo
      Pages 117-138

  4. EAMA: 3rd Workshop for Emerging Applications and Many-Core Architectures

    1. Parallelization of Particle Filter Algorithms

      • Matthew A. Goodrum, Michael J. Trotter, Alla Aksel, Scott T. Acton, Kevin Skadron
      Pages 139-149

    2. What Kinds of Applications Can Benefit from Transactional Memory?

      • Mark Moir, Dan Nussbaum
      Pages 150-160

    3. Characteristics of Workloads Using the Pipeline Programming Model

      • Christian Bienia, Kai Li
      Pages 161-171

  5. WEED: 2nd Workshop on Energy Efficient Design

    1. The Search for Energy-Efficient Building Blocks for the Data Center

      • Laura Keys, Suzanne Rivoire, John D. Davis
      Pages 172-182

    2. KnightShift: Shifting the I/O Burden in Datacenters to Management Processor for Energy Efficiency

      • Sabyasachi Ghosh, Mark Redekopp, Murali Annavaram
      Pages 183-197

    3. Guarded Power Gating in a Multi-core Setting

      • Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram
      Pages 198-210

    4. Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors

      • Ali Shafiee, Narges Shahidi, Amirali Baniasadi
      Pages 211-221

    5. Achieving Power-Efficiency in Clusters without Distributed File System Complexity

      • Hrishikesh Amur, Karsten Schwan
      Pages 222-232
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Other volumes

  1. Computer Architecture

Editors and Affiliations

  • Software Technologies Department, Delft University of Technology, Delft, The Netherlands

    Ana Lucia Varbanescu

  • Software Technologies Dept, Delft University of Technology, Delft, The Netherlands

    Anca Molnos

  • Department of Computer Science, Vrije Unversiteit Amsterdam, Amsterdam, The Netherlands

    Rob Nieuwpoort

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