Abstract
NoC-based manycore chips are considered as emerging platforms of significant importance but so far there is no public accessible architectural simulator which allows coupled simulation of NoC and cores for relevant research. This paper presents a modular cycle-level simulator framework developed using UNISIM and its applicability is exemplified by building a simulator which models a message-passing distributed memory architecture with an NoC and supports coupled simulation. Simulation of a MPI-based parallel program on this simulator shows that performance metrics, such as throughput, delay and overhead, can be accurately evaluated with the captured data of flits and messages. Simulators for different functionalities and architectures can be constructed by using this framework.
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Liao, X., Jigang, W., Srikanthan, T. (2011). A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers IV. Lecture Notes in Computer Science, vol 6760. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24568-8_12
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DOI: https://doi.org/10.1007/978-3-642-24568-8_12
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