Abstract
In this paper we present a new approach to minimize costs for partial dynamic reconfiguration of FPGAs. First, we develop a general Module Transition Model (MTM). In the MTM the reconfiguration is modeled at the granularity of reconfigurable resources, hence the model can take advantage of the partially identical configurations. The MTM targets both, minimum reconfiguration time and data. After it, the MTM is used at two diffent levels: (1) We apply the MTM to minimize binary configuration data, i.e. to generate cost efficient bitstreams for reconfigurable systems. It is shown how our model relates to previously established reconfiguration techniques. The improvements in reconfiguration time and bitstream size are demonstrated on an example. (2) We apply the MTM for high level designs, as the model also provides a measure for the similarity of reconfigurable circuits. The model describes in detail, which circuit elements are static and which need to be reconfigured. We use the model to derive a cost function in a high level synthesis tool to derive an allocation with minimal reconfiguration costs.
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Rullmann, M., Merker, R. (2011). A Cost Model for Partial Dynamic Reconfiguration. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers IV. Lecture Notes in Computer Science, vol 6760. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24568-8_19
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DOI: https://doi.org/10.1007/978-3-642-24568-8_19
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