Abstract
The issue logic of a superscalar processor consumes a large amount of static and dynamic energy. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. This paper presents a novel approach to energy reduction that uses compiler analysis communicated to the hardware, allowing the processor to dynamically resize the issue queue, fitting it to the available ILP without slowing down the critical path. Limiting the entries available reduces the quantity of instructions dispatched, leading to energy savings in the banked issue queue without adversely affecting performance.
Compared with a recently proposed hardware scheme, our approach is faster, simpler and saves more energy. A simplistic scheme achieves 31% dynamic and 33% static energy savings in the issue queue with a 7.2% performance loss. Using more sophisticated compiler analysis we then show that the performance loss can be reduced to less than 0.6% with 24% dynamic and 30% static energy savings and an EDD product of 0.96, outperforming two current state-of-the-art hardware approaches.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Folegnani, D., González, A.: Energy-effective issue logic. In: ISCA-28 (2001)
Emer, J.: Ev8: The post-ultimate alpha. In: Keynote at PACT (2001)
Buyuktosunoglu, A., Schuster, S., Brooks, D., Bose, P., Cook, P., Albonesi, D.H.: An adaptive issue queue for reduced power at high performance. In: Falsafi, B., VijayKumar, T.N. (eds.) PACS 2000. LNCS, vol. 2008, p. 25. Springer, Heidelberg (2001)
Abella, J., González, A.: Power-aware adaptive issue queue and register file. In: Pinkston, T.M., Prasanna, V.K. (eds.) HiPC 2003. LNCS (LNAI), vol. 2913, pp. 34–43. Springer, Heidelberg (2003)
Bahar, R.I., Manne, S.: Power and energy reduction via pipeline balancing. In: ISCA-28 (2001)
Maro, R., Bai, Y., Bahar, R.I.: Dynamically reconfiguring processor resources to reduce power consumption in high-performance processors. In: Falsafi, B., VijayKumar, T.N. (eds.) PACS 2000. LNCS, vol. 2008, p. 97. Springer, Heidelberg (2001)
Manne, S., Klauser, A., Grunwald, D.: Pipeline gating: Speculation control for energy reduction. In: ISCA-25 (1998)
Buyuktosunoglu, A., Karkhanis, T., Albonesi, D.H., Bose, P.: Energy efficient co-adaptive instruction fetch and issue. In: Falsafi, B., VijayKumar, T.N. (eds.) PACS 2000. LNCS, vol. 2008. Springer, Heidelberg (2001)
Canal, R., González, A.: Reducing the complexity of the issue logic. In: ICS-15 (2001)
Huang, M., Renau, J., Torrellas, J.: Energy-efficient hybrid wakeup logic. In: ISLPED (2002)
Önder, S., Gupta, R.: Superscalar execution with dynamic data forwarding. In: PACT (1998)
Palacharla, S., Jouppi, N.P., Smith, J.E.: Complexity-effective superscalar processors. In: ISCA-24 (1997)
Abella, J., González, A.: Low-complexity distributed issue queue. In: HPCA-10 (2004)
Ernst, D., Hamel, A., Austin, T.: Cyclone: A broadcast-free dynamic instruction scheduler with selective replay. In: ISCA-30 (2003)
Hu, J.S., Vijaykrishnan, N., Irwin, M.J.: Exploring wakeup-free instruction scheduling. In: HPCA-10 (2004)
Lee, C., Lee, J.K., Hwang, T., Tsai, S.-C.: Compiler optimization on instruction scheduling for low power. In: ISSS-13 (2000)
Lorenz, M., Leupers, R., Marwedel, P., Dräger, T., Fettweis, G.: Low-energy DSP code generation using a genetic algorithm. In: ICCD-19 (2001)
Zhang, W., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Duarte, D., Tsai, Y.-F.: Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. In: MICRO-34 (2001)
Toburen, M.C., Conte, T.M., Reilly, M.: Instruction scheduling for low power dissipation in high performance microprocessors. Technical report, North Carolina State University (1998)
Magklis, G., Scott, M.L., Semeraro, G., Albonesi, D.H., Dropsho, S.: Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor. In: ISCA-30 (2003)
Bellas, N., Hajj, I., Polychronopoulos, C., Stamoulis, G.: Energy and performance improvements in microprocessor design using a loop cache. In: ICCD-17 (1999)
Hsu, C.-H., Kremer, U., Hsiao, M.: Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors. In: ISLPED (2001)
Jones, T.M., O’Boyle, M.F.P., Abella, J., González, A., Ergin, O.: Compiler directed early register release. In: PACT (2005)
Lo, J.L., et al.: Software-directed register deallocation for simultaneous multithreaded processors. IEEE TPDS 10(9) (1999)
Jones, T.M., O’Boyle, M.F.P., Abella, J., González, A.: Software directed issue queue power reduction. In: HPCA-11 (2005)
Tullsen, D.M., Calder, B.: Computing along the critical path. Technical report, University of California, San Diego (1998)
Fields, B., Rubin, S., Bodík, R.: Focusing processor policies via critical-path prediction. In: ISCA-28 (2001)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: ISCA-27 (2000)
Burger, D., Austin, T.: The simplescalar tool set, version 2.0. Technical Report TR1342, University of Wisconsin-Madison (1997)
Smith, M.D., Holloway, G.: The Machine-SUIF documentation set (2000), http://www.eecs.harvard.edu/machsuif/software/software.html
The Stanford SUIF Compiler Group: The suif compiler infrastructure, http://suif.stanford.edu/
The Standard Performance Evaluation Corporation (SPEC): CPU 2000 (2000), http://www.spec.org/cpu2000/
Abella, J., González, A.: Power-aware adaptive instruction queue and rename buffers. Technical Report UPC-DAC-2002-31, UPC (2002)
Aygün, K., Hill, M.J., Eilert, K., Radhakrishnan, K., Levin, A.: Power delivery for high-performance microprocessors. Intel Technology Journal 9(4) (2005)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Jones, T.M., O’Boyle, M.F.P., Abella, J., González, A. (2011). Compiler Directed Issue Queue Energy Reduction. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers IV. Lecture Notes in Computer Science, vol 6760. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24568-8_3
Download citation
DOI: https://doi.org/10.1007/978-3-642-24568-8_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-24567-1
Online ISBN: 978-3-642-24568-8
eBook Packages: Computer ScienceComputer Science (R0)