Abstract
Memory-CPU single communication channel bottleneck of the von Neumann architecture is quickly stalling the growth of computer processors. A probable solution to this problem is to fuse processing and memory elements. A simple low latency single on-chip memory and processor cannot solve the problem as the fundamental channel bottleneck will still be there due to the logical splitting of processor and memory. This paper presents that a paradigm shift is possible by combining Arithmetic logic unit and Random Access Memory (ARAM) elements at bit level. This bit level modest ARAM is used to perform word level ALU instructions with minor modifications. This makes the ARAM cells capable of executing instructions in parallel. It is also asynchronous and hence reduces power consumption significantly. A CMOS implementation is presented that verifies the practicality of the proposed ARAM.
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References
Backus, J.: Can programming be liberated from the von neumann style? a functional style and its algebra of programs. Communications of the ACM 21(8), 613–641 (1978)
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Francisco (1990)
Furber, S., Brown, A.: Biologically-inspired massively-parallel architectures - computing beyond a million processors. In: International Conference on Application of Concurrency to System Design, pp. 3–12 (2009)
Stone, H.S.: A logic-in-memory computer. IEEE Transactions on Computers, 73–78 (January 1970)
Elliott, D.G.: Computational RAM: A memory-SIMD Hybrid. PhD thesis, University of Toronto, Pasadena, California (December 1997)
Gokhale, M., Holmes, B., Iobst, K.: Processing in memory: The terasys massively parallel PIM array. IEEE Computer, 22–31 (April 1995)
Patterson, D., Anderson, T., Cardwell, N., Fromm, R., Keeton, K., Kozyrakis, C., Thomas, R., Yelick, K.: A case for intelligent ram. IEEE Micro, 34–44 (April 1997)
Geer, D.: Is it time for clockless chips? IEEE Computer, 18–19 (March 2005)
Paver, N.C.: The design and implementation of an asynchronous microprocessor. PhD thesis, University of Manchester (1994)
Rahman, M.Z.: A recursive approach to the design of parallel self-timed adders. University of Malaya, Tech. Rep. (2010), http://web.fsktm.um.edu.my/~zia/TR/PASTA-TR-2010.PDF
Sutherland, I.E.: Micropipelines. Communications of ACM 32(6), 720–738 (1989)
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Rahman, M.Z. (2011). A Combined Arithmetic Logic Unit and Memory Element for the Design of a Parallel Computer. In: Xiang, Y., Cuzzocrea, A., Hobbs, M., Zhou, W. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2011. Lecture Notes in Computer Science, vol 7016. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24650-0_26
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DOI: https://doi.org/10.1007/978-3-642-24650-0_26
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