Skip to main content

State Encoding and Minimization Methodology for Self-Checking Sequential Machines

  • Conference paper
Computer Aided Systems Theory – EUROCAST 2011 (EUROCAST 2011)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6927))

Included in the following conference series:

Abstract

State encoding methodology and minimization procedure for designing of reliable digital circuit - Totally Self Checking Sequential Machines is considered in this article. We limit considerations to Mealy sequential circuits with inputs, internal states and outputs encoded with any unordered code.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Anderson, D.A., Metze, G.: Design of totally self-checking check circuits for m-out-of-n codes. IEEE Transactions on Computers C-22, 263–269 (1973)

    Article  Google Scholar 

  2. Carter, W.C., Schneider, P.R.: Design of dynamically checked computers. In: Proceedings IFIP Conference, Edinburgh, Scotland, pp. 878–883 (August 1968)

    Google Scholar 

  3. David, R., Thevenod-Fosse, P.: Design of totaly self-checking asynchronous modular circuits. J. Des. Autom. Fault-Tolerant Comput. 2, 271–278 (1978)

    Google Scholar 

  4. Diaz, M., de Souza, J.M.: Design of self-checking microprogrammed controls. In: Digest of Papers 5th International FTC Symposium, Paris, France, pp. 1371–142 (June 1975)

    Google Scholar 

  5. Greblicki, J.W., Piestrak, S.J.: Design of totally self-checking code-disjoint synchronous sequential circuits. In: Hlavicka, J., Maehle, E., Pataricza, A. (eds.) EDDC 1999. LNCS, vol. 1667, pp. 251–266. Springer, Heidelberg (1999)

    Google Scholar 

  6. Greblicki, J.W.: Synthesis of sequential circuits using unordered codes. PhD thesis, Wroclaw University of Technology, Wroclaw (October 2003) (in polish)

    Google Scholar 

  7. Greblicki, J.W.: CAD software for designing of totally self checking sequential circuits. In: DepCoS – RELCOMEX 2006, pp. 289–296. IEEE Computer Society Press, Los Alamitos (2006)

    Google Scholar 

  8. Greblicki, J.W., Kotowski, J.: Design of totally self-checking sequential circuits. In: 2nd International Symposium on Logistics and Industrial Informatics (LINDI), Linz, Austria (September 10-11, 2009)

    Google Scholar 

  9. Jha, N.K., Wang, S.-J.: Design and synthesis of self-checking VLSI circuits. IEEE Transactions on Computer–Aided Design of Integrated Circuits 12, 878–887 (1993)

    Article  Google Scholar 

  10. Lai, C.-S., Wey, C.-L.: An efficient output function partitioning algorithm reducing hardware overhead in self-checking circuits and systems. In: Proceedings of 35th Midwest Symposium Circuits System, pp. 1538–1541 (1992)

    Google Scholar 

  11. Piestrak, S.J.: PLA implementation of totally self-checking circuits using m-out-of-n codes. In: Proceedings ICCD 1985, International Conference on Computer Design: VLSI in Computers, Port Chester, N.Y, October 1-3, pp. 777–781 (1985)

    Google Scholar 

  12. Smith, J.E.: The design of totally self-checking check circuits for a class of unordered codes. J. Des. Autom. Fault–Tolerant Comput. 2, 321–342 (1977)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Brzozowska, A., Greblicki, J., Kotowski, J. (2012). State Encoding and Minimization Methodology for Self-Checking Sequential Machines. In: Moreno-Díaz, R., Pichler, F., Quesada-Arencibia, A. (eds) Computer Aided Systems Theory – EUROCAST 2011. EUROCAST 2011. Lecture Notes in Computer Science, vol 6927. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27549-4_71

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-27549-4_71

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-27548-7

  • Online ISBN: 978-3-642-27549-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics