Abstract
FPGA-based processor prototyping system can fast simulate processor behavior and enables longer time simulations to obtain useful evaluation information. In this paper we present ScalableCore system 3.3, which is an FPGA-based simulator of NoC-based tile architectures by employing multiple Xilinx Spartan-6 FPGAs. Two key techniques enable the system to achieve scalable speed of simulations by using corresponding amount of FPGAs to the target number of processor cores. We evaluated behavior of a processor consisting of 100 cores and a mesh NoC by using our developed system. The simulation speed is 129 times faster than the one of a software-based simulator running on a standard computer of Core i7 processor.
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Takamaeda-Yamazaki, S., Sano, S., Sakaguchi, Y., Fujieda, N., Kise, K. (2012). ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. In: Choy, O.C.S., Cheung, R.C.C., Athanas, P., Sano, K. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2012. Lecture Notes in Computer Science, vol 7199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28365-9_12
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DOI: https://doi.org/10.1007/978-3-642-28365-9_12
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