Abstract
The future high-end embedded systems applications are characterized by their computation-intensive workloads, their high-level of parallelism, their large data-set requirements, and their dynamism. Those applications require highly-efficient manycore architectures. In response to this problem, we designed an asymmetric homogeneous with dynamic allocator manycore architecture, called AHDAM chip. AHDAM chip exploits the parallelism on all its granularity levels. It implements multithreading techniques to increase the processors’ utilization. We designed an easy programming model and reused an automatic compilation and application parallelization tool. To study its performance, we used the radio spectrum sensing application from the telecommunication domain. On a simulation framework, we evaluated sequential and parallel versions of the application on 2 platforms: single processor, and AHDAM chip with a variable number of processors. The results show that the application on the AHDAM chip has an execution time 574 times faster than on the single-processor system, while meeting the real-time deadline and occupying 51.92 mm2 at 40 nm technology.
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Duranton, M., Yehia, S., De Sutter, B., De Bosschere, K., Cohen, A., Falsafi, B., Gaydadjiev, G., Katevenis, M., Maebe, J., Munk, H., Navarro, N., Ramirez, A., Temam, O., Valero, M.: The HiPEAC Vision. HiPEAC Network of Excellence (2010)
Lacassagne, L., Zavidovique, B.: Light speed labeling: efficient connected component labeling on RISC architectures. Journal of Real-Time Image Processing, 1–19 (2009), doi:10.1007/s11554-009-0134-0
Wall, D.W.: Limits of instruction-level parallelism. In: Int’l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Santa Clara, USA (April 1991)
Bertogna, M., Cirinei, M., Lipari, G.: Schedulability Analysis of Global Scheduling Algorithms on Multiprocessor Platforms. IEEE Transactions on Parallel and Distributed Systems 20(4), 553–566 (2008)
Ventroux, N., David, R.: The SCMP architecture: A Heterogeneous Multiprocessor System-on-Chip for Embedded Applications. Eurasip (2009)
HPC Project: PAR4ALL tool, http://hpc-project.com/pages/par4all.htm
OpenMP, http://www.openmp.org
Muralimanohar, N., Balasubramonian, R.: CACTI 6.0: A Tool to Model Large Caches
Riley, M.W., Warnock, J.D., Wendel, D.F.: Cell Broadband Engine processor: Design and implementation. IBM Journal of Research and Development 51(5), 545–557 (2007)
Guerre, A., Ventroux, N., David, R., Merigot, A.: Hierarchical Network-on-Chip for Embedded Many-Core Architectures. In: 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 189–196 (May 2010)
Bechara, C., Ventroux, N., Etiemble, D.: Comparison of different thread scheduling strategies for Asymmetric Chip MultiThreading architectures in embedded systems. In: 14th Euromicro Conference on Digital System Design (DSD 2011), Oulu, Finland (September 2011)
Ventroux, N., Sassolas, T., David, R., Blanc, G., Guerre, A., Bechara, C.: SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications. In: 2010 18th IEEE/IFIP on VLSI System on Chip Conference (VLSI-SoC), pp. 341–346 (September 2010)
Bechara, C., Ventroux, N., Etiemble, D.: Towards a Parameterizable cycle-accurate ISS in ArchC. In: IEEE International Conference on Computer Systems and Applications (AICCSA), Hammamet, Tunisia (May 2010)
Middha, B., Gangwar, A., Kumar, A., Balakrishnan, M., Ienne, P.: A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units, pp. 2–7 (2002)
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Bechara, C., Ventroux, N., Etiemble, D. (2012). AHDAM: An Asymmetric Homogeneous with Dynamic Allocator Manycore Chip. In: Keller, R., Kramer, D., Weiss, JP. (eds) Facing the Multicore - Challenge II. Lecture Notes in Computer Science, vol 7174. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-30397-5_5
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DOI: https://doi.org/10.1007/978-3-642-30397-5_5
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