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A Tunable CMOS Continuous-Time Filter Designed for a 5.8 GHz ETC Demodulator

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Wireless Internet (WICON 2011)

Abstract

5.8 GHz is specified as the operating frequency of the electronic tolling collection (ETC) system in the new national highway network in China. A low power, robust radio frequency receiver is the key design challenge in such a system. A 3rd order butterworth low-pass filter with tunable pass-band designed for the ETC receiver was presented in this work. The design is based on a single operational amplifier in order to reduce the overall power consumption. The filter was implemented in standard CMOS 0.18 μm technology. Simulation shows that the design achieves a maximum 3-dB bandwidth of 2 MHz with 0 dB insertion loss, while the power consumption is only ~200μW.

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References

  1. GB/T 20851-2007, Electronic toll collection-Dedicated short range communication Interface with Roadside Unit and Lane Controller (2007)

    Google Scholar 

  2. Thede, L.: Practical Analog And Digital Filter Design. Artech House (2004)

    Google Scholar 

  3. Fan, X.H., Mishra, C., Edgar, S.S.: Single Miller Capacitor Frequency Compensation Technique for Low-Power Multistage Amplifiers. IEEE Journal of Solid-state Circuits 40(3), 584–592 (2005)

    Article  Google Scholar 

  4. Winder, S.: Analog and Digital Filter Design. Newnes (2002)

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  5. Allen, P.E., Holberg, D.R.: CMOS analog circuit design. PHEI, Beijing (2002)

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© 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering

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Yu, H., Jiang, L., Lin, S., Li, Y., Wei, R., Ji, Z. (2012). A Tunable CMOS Continuous-Time Filter Designed for a 5.8 GHz ETC Demodulator. In: Ren, P., Zhang, C., Liu, X., Liu, P., Ci, S. (eds) Wireless Internet. WICON 2011. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 98. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-30493-4_53

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  • DOI: https://doi.org/10.1007/978-3-642-30493-4_53

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-30492-7

  • Online ISBN: 978-3-642-30493-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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